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New programmable device family combines CPLD, FPGA features

Posted: 22 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:field-programmable gate array? fpga? lattice semiconductor? machxo? programmable logic device?

Combines PLD, and FPGA technologiesIn its third major and FPGA announcement in the last 12 months, Lattice Semiconductor Corp. has introduced MachXO, a new product family that combines the key features of complex programmable logic device (PLD) and FPGA technologies in a single device.

Lattice has two parts immediately available, the MachXO256 and MachXO640. Like much of the PLD market, Lattice is pushing the MachXO family into several sectors, including telecommunications, computing, communications, medical and industrial.

"These MachXO products are based on the embedded flash and SRAM technology," said Stan Kopec, vice president of corporate marketing at Lattice. "By combining some of the best attributes of CPLD technology and FPGA architecture, we've got a new type of device that we call a crossover programmable logic device because it really stands applications that in the past high-end CPLDs or low-density FPGAs would have been used for."

Using 130nm non-volatile embedded flash process technology, Lattice designed its MachXO family to address reverse bridging, bus interfacing and control logic in a broad range of applications. What does it take to solve reverse bridging, bus interfacing and control logic? There are a variety of requirements that typically come up, according to Gordon Hands, strategic marketing manager at Lattice, who's responsible for the new product launch.

Hand cited several requirements, including a lot of I/Os relative to the amount of logic; the ability to easy and flexibly buffer data with temporary storage; fast pin-to-pin speeds to match microprocessor timing; and upgradeability to easily change logic. He also mentioned instant-on capability to have the logic available as the system powers up so that when the user, for instance, does the address decoding on the bus, he or she can make sure that nothing is accidentally selected, as well as low power.

"We've been able to address all of these in the MachXO. And we've been able to do it by combining features of the FPGA and CPLD domains," Hand said. "As we look at the CPLD domain, people expect high pin-to-pin speeds, fast white logic, which takes a lot of inputs and act on them very quickly, have a high I/O to logic ration and instant-on capabilitythese are key benefits of the CPLD products."

The MachXO family takes on several FPGA characteristics. MachXO devices are SRAM based, register intensive with a flexible memory architecture, and support embedded memory.

Since the MachXO devices are non-volatile and SRAM-based, they are highly secure. Data transfer is done inside the device, Hand said.

"In the FPGA arena, traditionally, people use look-up tables (LUT), and if you want to build a big function you have to chain them together. What we're finding is as the silicon gets faster and faster, and the interconnect gets faster and faster, people are finding that it's fine to build these wide functions by combing these small functions together," he said.

The MachXO announcement is Lattice Semiconductor's third in the field-programmable gate array (FPGA) market over the last 12 months. With Fujitsu as its foundry partner, the third largest programmable logic device (PLD) vendor has been able to make a big push in the sector. Last year, it introduced a low-cost FPGA, the LatticeEC/ECP that offers superior DDR memory support and DSP functions, as well as configuration options. And shortly after, it announced a non-volatile FPGA, the LatticeXP that is a single-chip device that is configured with its TransFR technology.

The MachXO family also features the company's TransFR technology, which allows engineers to update logic and designs in the field without taking their systems off-line, which is becoming increasingly important in the telecommunications, networking and server applications, Hand said.

More features
The MachXO family of devices is based on an LUT-based architecture. With the use of 4-input LUTs to implement logic, as well as non-volatile flash plus SRAM technology, the devices are 50 percent cheaper per logic function compared with CPLDs, Hand said.

The technology uses a native 1.2V logic core that is supply by 'E' versions of the MachXO devices for the lowest power consumption. An on-chip voltage regulator allows 'C' versions of the device to support 1.8-, 2.5- or 3.3V external power supplies to support legacy system power requirements.

At the core of each device is an array of look-up tables that can be used to implement logic and small distributed memories. The array is surrounded by flexible I/Os that can implement a variety of popular I/O standards, such as LVCMOS and, on the larger devices, PCI and LVDS. It features high-performance, 3.5ns pin-to-pin speeds, and is I/O intensive with between 78 and 271 I/Os.

Four density levels have been defined for the MachXO family256, 640, 1200 and 2280 LUT devices. The MachXO1200 and MachXO2280 support one or two analog PLLs, as well as one or three 9K-bit embedded block RAM blocks, respectively, yielding 9.2-K or 27.6K bits of block of memory per device.

Pricing and availability
Samples of the MachXO256 and MachXO640 are available now. Production quantities will be available in the third quarter of this year. In quantities of 250,000 and more, the MachXO256 will be priced at $1.50 and the MachXO640 at $2.25 each.

Samples of MachXO1200 and MachXO2280 will be available in the second half of 2005, with production slated for the fourth quarter of 2005 and the first quarter of 2006, respectively.

Package options include thin quad flatpack (TQFP), 8-by-8mm footprint chip-scale BGA and fine pitch BGA package styles from 100 to 324 leads.

- Ismini Scouras
eeProductCenter




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