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UMC, Virage Logic to enable optimal IP development

Posted: 25 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:virage logic? silicon aware ip? ip? circuit design? 65nm?

Taiwan-based semiconductor foundry United Microelectronics Corp. and Virage Logic Corp., a pioneer in Silicon Aware IP, have announced an agreement where Virage Logic will extend its IP and circuit design expertise to jointly work with UMC to enable optimal IP development for UMC's 65nm process technology.

The partnership will help accelerate adoption of UMC's next-generation technology platform and provide a predictable roadmap for enhancements of key IP structures such as memory bit cells.

The agreement calls for Virage Logic to collaborate and consult with UMC's technology and design support teams to analyze process parameters critical for design of key IP elements such as memory, logic and I/Os in order to optimize area, speed, performance and manufacturing yield of SoCs.

"At 65nm, design experts and process technology teams need to synchronize much earlier than previous generations to address the new challenges brought by the increasing complexities of deep sub-micron technology nodes," said Patrick T. Lin, chief SoC architect, system and architecture support group, UMC.

"Virage Logic's expertise and understanding of the relationship between advanced process parameters and semiconductor IP requirements will be a valuable asset to this effort, and we look forward to their contributions to help accelerate the acceptance of our 65nm process."

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