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AccelChip offering cores through Xilinx program

Posted: 29 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:field-programmable gate array? fpga? ip core?

Claiming to be the industry's first to do so, AccelChip Inc. said Wednesday (July 27) it has begun providing a family of fixed-point linear algebra intellectual property (IP) cores for Xilinx field-programmable gate array (FPGA) devices.

AccelChip said its matrix inverse and factorization cores are being offered through Xilinx' third-party Alliance Program.

According to AccelChip, the cores are the first of their kind and directly implement linear algebra-based matrix operations used in applications such as sensor array processing, beamforming, global positioning, radar/sonar, Kalman filtering and wireless communication applications.

"The addition of AccelCore into the Xilinx Alliance Program has the potential to save months of development time, regardless of design entry methodology with proven linear algebra-based matrix cores for advanced wireless and signal processing applications," said David Squires, director of DSP marketing at Xilinx, in a statement.

The initial offering of AccelCore DSP IP available through the Xilinx Alliance Program includes QR matrix factorization and inverse, Cholesky matrix factorization and inversion, and singular value decomposition (SVD).

Each AccelCore is available separately under the standardized Xilinx SignOnce IP license agreement, which offers customers a single set of licensing terms for acquiring FPGA-based IP cores from more than 55 third-party IP vendors.

- EE Times

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