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Synopsys test methodologies verify SLE's chip developments

Posted: 29 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:rtl verification solution? vera testbench automation tool? asic design? silicon logic engineering?

Synopsys Inc. announced that its VCS comprehensive RTL verification solution and Vera testbench automation tool have been adopted by ASIC design services provider Silicon Logic Engineering (SLE) to accelerate its chip development process.

SLE is apparently taking advantage of the Synopsys reference verification methodology (RVM) to reduce the development time for its verification environment and to ensure the highest-quality verification results. In addition to the VCS solution and Vera tool, SLE has adopted also Synopsys' Magellan hybrid formal analysis, Leda RTL checking and Formality formal equivalency checking solutions from the Discovery verification platform.

"We chose Synopsys as our verification partner on our latest 90-nanometer, 40-million-gate chip development project after evaluating several providers," said Bob Solberg, VP of operations and co-founder at SLE.

According to Solberg, Synopsys' RVM was able to cut their verification development time, while promoting industry best practices within their verification team.

The Synopsys reference verification methodology, delivered with VCS Native testbench technology and the Vera tool, helps engineers to quickly implement and deploy advanced verification environments using modern constrained-random, coverage-driven and assertion-based verification techniques.

The RVM speeds verification development by providing pre-defined base-class libraries with advanced features for transaction modeling, transactor construction, messaging services, verification flow and assertion checkers.

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