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Cutting RF power in W-CDMA phones

Posted: 01 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:rf? w-cdma? cdma? wireless? vref?

The spread-spectrum wireless communications standard IS-95/3GPP embodies stringent specifications for linearity and adjacent-channel power ratio (ACPR). To meet them, W-CDMA wireless handsets require highly linear Class A or Class AB RF power amplifiers. The power-added efficiency (PAE) for that type of power amplifier, however, is only about 35 percent maximum at an output power of 28dBm; for lower power levels, it is much less than that.

The power amplifier does not operate continuously in voice mode. When the phone user is not speaking, it runs at a half rate (50 percent of the time) or one-eighth rate, so there is no worry about the phone's heating during voice mode. But in data mode, the power amplifier runs continuously until data transmission is complete. Combining the power amplifier's low efficiency and continuous operation causes the battery to drain quickly, and the resulting internal power dissipation may also make the phone too hot.

Power dissipation was a major problem for early W-CDMA handsets that supported high-speed data transmission services. It obliged designers to include larger heat sinks to provide more airflow for cooling bigger batteries. Fortunately, this problem has been eased by an improvement in power amplifier efficiency for CDMA and W-CDMA cellphones.

In CDMA and W-CDMA systems, the power amplifier's RF power output is not always maximum. To optimize the cell capacity (number of simultaneous transmissions that a base station can handle), each mobile phone controls its RF output power so that the effective signal-to-noise level received at the base station is the same for each phone.

A probability distribution of the RF output-power levels from many phones in a given area shows that the average output power from a typical CDMA or W-CDMA phone is about 10dBm for suburban conditions and 5dBm for urban conditions. Thus, a useful target for improving power amplifier efficiency is not the maximum power level, but an approximate range of 5dBm to 10dBm.

Two supply voltages are required for the CDMA and W-CDMA power amplifier. Vref provides bias for the internal driver and power-amplifier stages, and Vcc biases the collectors for the driver and power amplifiers. We can reduce the power amplifier supply current by adjusting those two voltages.

When transmitting zero RF power, the power amplifier itself draws a typical quiescent current of 100mA at a Vref of 3V and Vcc equal to 3.4V. Reducing Vref from 3V to 2.9V causes the quiescent current to drop to about 20mA.

Thus, designers can achieve savings in power-amplifier quiescent current by lowering Vref, but not below the point at which the power amplifier linearity and ACPR begin to fail their specifications.

If we have experimental data giving the minimum Vref voltage required to support each output-power level slotted for the power amplifier, we can actively couple the control of Vref with the amplifier's power-control process. If that approach is too difficult, we can simply implement a two-step change in Vref that corresponds to the low-power (<10dBm) and high-power mode (>10dBm).

To adjust Vref via the baseband control DAC, we use a low-power op amp with high output-current capability, along with an external gain setting.

In typical wireless handsets, the power amplifier Vcc is delivered directly from a single-cell Li-ion battery, resulting in an operating Vcc range of 3.2V to 4.2V. As mentioned, statistics show that the CDMA and W-CDMA power amplifier operates at power levels of 5dBm to 10dBm most of the time.

At those levels, we can reduce the power amplifier Vcc considerably without losing linearity in the power amplifier and, at the same time, reduce the power loss from excessive collector-bias headroom.

Based on experimental tests at low-power levels, we can maintain proper communications with the base station while lowering the power amplifier collector bias all the way down to 0.6V.

A variable bias voltage for the power amplifier collector is provided by a specially designed, high-efficiency dc-dc step-down converter.

We adjust the output voltage of this converter using a dedicated D/A output from the baseband processor.

The dc-dc converter controlling the power amplifier collector voltage must respond quickly to a control signal. Usually, the converter's output voltage should settle to within 90 percent of its new target voltage within 30ms following a change in analog control voltage from the baseband processor.

The converter chip provides an appropriate internal gain between its Vcccontrol I/O voltage that biases the power amplifier collector. It also switches at HF to reduce the physical size of the inductor.

Connecting the dc-dc converter between power amplifier and battery highlights a problemi.e. the demand for high RF power at low battery voltage. To deliver 28dBm RF power while maintaining the specification for power amplifier linearity, manufacturers recommend a minimum Vcc of 3.4V. To maintain a 35 percent PAE at 3.4V, we also need a high power amplifier collector current of 530mA:

28dBm RF power: 102.8mW = 631mW.

Required power amplifier power (Vcc x Icc): 631mW/(PAE/100) = 1,803mW.

Required power amplifier Icc at 3.4V Vcc: Icc = 1,803mW/3.4V = 530mA.

To support a 3.4V Vcc and 530mA Icc, the dc-dc converter for the power amplifier power requires a certain amount of input-to-output headroom.

If, for example, on-resistance for the converter's internal p-channel MOSFET (PFET) is 0.4 ohm and the inductor resistance is 0.1 ohm, the voltage drop across those two components in series will be (0.4 ohm + 0.1 ohm) * 530mA = 265mV. Thus, the dc-dc converter is unable to support a 3.4V output when the battery voltage drops below 3.665V.

In this case (battery voltage less than 3.665V), it is better to short the power amplifier collector to the battery. Otherwise, we cannot access the full capacity of the Li-ion battery.

Normally, the solution is to bypass the inductor and internal PFET by connecting a low-Rds(on) PFET in parallel. This bypass PFET (which can be internal or external) connects battery voltage directly to the power amplifier collector when in the high-power mode. For the combination of high RF power and low battery voltage, this bypass measure is a must-do.

- Jay Kim

Corporate Application Engineer

Maxim Integrated Products Inc.

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