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Little time, big decisions for 45nm node

Posted: 01 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:45nm? high-k dielectric? metal gate electrode? 2005 symposium on vlsi technology?

Technologists will have to face some tough decisions in the coming weeks and months as they ponder which knobs to turn for the 45nm node. With gains from gate oxide scaling and shorter channel lengths at a near standstill, process engineers are looking to a much different list of "boosters," including further pushing strain in the silicon channels and high-k dielectrics with metal gate electrodes.

The toughest nut to crack, experts at the 2005 Symposium on VLSI Technology said, is no longer the high-k gate oxide, but which metal gate electrodes to use!in combination with the hafnium-based high-k oxides!to set and maintain the correct threshold voltages.

And time is running short, making it likely that most companies will not use a high-k solution, at least not in the first go-round of the 45nm node. "We've got about two weeks to decide on our high-performance process," said Scott Crowder, director of the 45nm process development effort at IBM Corp. High-k remains an option, he said, but a solution needs to come soon.

Mark Bohr, director of processor architecture and integration at Intel Corp., said the company's microprocessor design teams by this point in the two-year logic technology cycle would have expected to receive transistor information and layout design rules for the 45nm node.

"We are really being pressed by the clock," he said.

If Intel is to continue its normal two-year cycle between nodes, Bohr said, it must make decisions soon about the gate stack, particularly on whether to use a high-k oxide with metal gates. And that involves a related choice: whether to use different deposited metals at the NMOS and PMOS transistors or to rely on a fully silicided (FUSI) process that replaces the polysilicon electrode with nickel or another silicideable metal that can be doped and tuned for the right work functions.

Intel still hasn't developed a complete high-k-oxide, metal gate solution for the 45nm node, Bohr said, though it is "narrowing down its options."

Intel has taken multigate devices off the 45nm table, Bohr said. Two years ago, multigate transistors were seen as an alternative for improving drive current, in case a high-k solution was not ready for 45nm. Among the multigate challenges, he said, is controlling the width of the narrow fin.

While it would be possible to continue to use the conventional nitrided gate oxide with a polysilicon gate electrode for the 45nm node, Bohr said, "in my view, we can do better than that."

That makes it imperative to find a good metal for the gate electrode. "We are still interested in FUSI," Bohr said, partly because that method has shown less process complexity than depositing two different metals at the gate electrode. "It's hard to get the exact work function we need with FUSI, but it is not impossible."

Frustration on metal progress

Technology managers said they are encouraged by the progress shown with hafnium-based oxides in terms of reliability, leakage mobility and electrical oxide thickness. What is lacking is the ability to fix and maintain the Vt, which depends on getting the right metal electrode to set the work function as near to the edge of the bandgap as possible.

At the VLSI Technology symposium, several technology managers agreed that the Kyoto meeting demonstrated little progress in the search for a metal gate. Sufi Zafar, an advanced gate dielectrics researcher at IBM's T.J. Watson Research Center, said her industry "thus far cannot find the right metals. All of these companies have been doing wafer splits for four years now, all over the world, and yet we still only have midgap metals. We need to come up with methods to get there faster."

Zafar has proposed that companies adopt research methods!based on theories developed in the 1960s, but stumbled upon only recently!that would provide understandable data to the gate oxide/metal gate research community. "We have to get the industry to focus on what the problems are, which are fixed charges in the oxide and setting the work function with the metal gate. Right now, the numbers from different companies are all over the map; it's all process-dependent."

Jorge Kittl, a Texas Instruments Inc. gate oxide researcher assigned to the Interuniversity Microelectronics Center consortium in Leuven, Belgium, presented results from an IMEC study of FUSI metal gates that he said showed "good progress, though we haven't seen any breakthroughs. Interest is high from the companies needing a low-power solution, but for the high-performance applications, we still need to get the threshold voltages lower to get a little more swing on both the NMOS and PMOS."

Byoung Hun Lee, an IBM assignee to International Sematech who manages the advanced gate stack program, said he believes that "by the end of this year, we can deliver a high-k/metal gate solution to our Sematech member companies. There is a fair chance that we can deliver it in time for companies to use high-k at the 45nm node by 2007."

Lee added that Sematech has "identified, but has not disclosed," a good candidate metal for the PMOS gate electrode.

The search for the appropriate metal for the NMOS metal gate, "is a little more difficult," he said. While many companies favor a FUSI approach, Lee thinks FUSI is "not manufacturing-friendly."

HOT debate on orientation

With performance at a premium at Big Blue, IBM has developed one process module that it claims is ahead of the rest of the industry!a hybrid orientation technology (HOT) that provides a major boost for PFET performance. HOT combines 110-oriented silicon in the PFET regions, with 100-oriented silicon for the NFET.

Is the extra process complexity worth the roughly 14 percent ring oscillator performance gain?

Meikei Ieong, a senior manager of exploratory device research at IBM, said selective epitaxial growth of 110 silicon at the PFET regions may sound difficult. But he argued that the additional complexity compares in difficulty to the added process steps needed to achieve strained silicon: either selective deposition of SiGe in the source and drain (the form that Intel introduced at the 90nm node), or the dual-stress liner approach to strained silicon taken by IBM and AMD.

David Fried, the IBM logic device design manager who presented HOT to the symposium, said that "HOT is definitely a challenging technology, particularly the selective silicon epitaxy in the PFET areas. For designers, it means different circuits because one transistor is in bulk and one is in silicon-on-insulator. But it provides a 30 percent improvement in the PFET on-current, which is huge."

Will IBM bring HOT in at the 45nm node? Fried said HOT is being evaluated "as a serious contender. It is very product-sensitive. All the materials are conventional, so it's just a materials integration challenge."

- David Lammers

EE Times





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