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RF IC tools still seeking paths to silicon

Posted: 01 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:rf block? wireless? harmonics? mixer? oscillator?

Radio-frequency (RF) design tools that help engineers visualize the performance of RF blocks are capitalizing on two trends: the popularity of all things wireless and the availability of more powerful computing platforms that are able to simulate the performance of much larger circuits.

But RF tool developers also have some hurdles to overcome as they introduce new products at the 42nd Design Automation Conference and the IEEE MTT-S 2005 International Microwave Symposium. The problem is ensuring the accuracy of the device models for CMOS fabrication. Many of these models have not been fully characterized for operation at 2GHz or 3GHz.

Complicated by multiple modulation schemes, RF tools have become proficient at simulating behavior on an architectural level. The harmonics generated by a power amplifier or the center frequency for a mixer-oscillator combination can be visualized very clearly by making certain assumptions about the parametric performance of those blocks. But where the designer needs to verify this with an actual silicon implementation, the RF tools link into other platforms and tools that are loaded with foundry model libraries and are proficient at IC design and layout.

Companies like Agilent Technologies' EEsof EDA products group, Ansoft and Applied Wave Research have evolved two types of RF design platforms. One is geared toward tweaking geometry-sensitive microwave- and millimeter-wave ICs and RF modules. The other involves RF IC design tools, which often link with platform tools from Cadence Design Systems Inc.

Agilent EEsof EDA is the fifth-largest EDA tool supplier, in Gartner Dataquest's estimates. The company dominates the RF design segment, with a 71 percent market share. Its tools include the RF Design Environment, for RF IC design, and the Advanced Design System, used by microwave designers for tuning RF transistors and layout-sensitive modules with few transistors. New additions to this product line include a heterojunction bipolar transistor model for GaAs and indium phosphide, developed in conjunction with the University of California, San Diego.

But model libraries remain a major challenge. Tool vendors must build and maintain model libraries that support RF standardseven new ones. These include test and verification suites that confirm whether a system will conform to a standard.

The toughest problem is modeling actual devices in a particular fabrication process. "This makes the designers dependent on the process design kits (PDKs) they get from silicon foundries and GaAs process vendors," said Joe Civello, product marketing manager at Agilent.

A number of tools are available to help designers create those models. Agilent's Advanced Model Composer, used with both the Advanced Design System and the RF Design Environment, uses a Verilog-A compiler. Designers can then use the models they develop to fine-tune a circuit to the standard, Civello said.

Which domain?

Ansoft Corp., which has 11 percent of the RF EDA tools market according to Dataquest, excels at electromagnetic simulationsthe kind that visualize the RF radiation patterns about an antenna or the trace lines on a PCB.

Like Agilent, the company is making a turn toward RF IC design and integration with the Cadence Design platform. Cadence's SpectreRF tool for time-domain analysis is especially useful for amplitude-transient analysis, said Ansoft business development director Larry Williams. But RF phenomena like harmonic distortion, phase noise or third-order intercept point are all calculated in the frequency domain, Williams said, so designers need a simulator that will do both. The latest version of Ansoft's Nexxim tools demonstrated at the Design Automation Conference is fully integrated with the Cadence platform.

Also courting RF IC designers is Applied Wave Research (AWR). The pressure to integrate RF Tx/Rx blocks with other CMOS processing elements is driving AWR's RF tool development toward full-blown IC design, said Tom Quan, the company's director of marketing.

Like Agilent's tools, AWR's offerings are now split between traditional microwave transistor tweaking, via its Microwave Office suite, and RF IC design, through Analog Office. The latter also links into Cadence's Virtuoso IC design platform.

Both Microwave Office and Analog Office depend on the availability of models. For RF ICs, designers are dependent on PDKs that are, ideally, fully characterized by the foundries. But the 0.18?m and 0.13?m geometry CMOS processes increasingly used for RF IC design, Quan said, are often not fully characterized for RF operation.

AWR tools, Quan said, model many current devices and provide the test structures for them. Analog Office allows designers to run full simulations with worst-case corners, he said.

Other pathways

While custom silicon has always been its goal, the software tools of Eagleware-Elanix Corp. have provided guideposts toward FPGA and DSP program implementations.

The latest version of the company's Genesys tools enhances the development of system blocks by expanding synthesis model libraries. The mixer synthesis module, for example, allows users to visualize the behavior of various mixer configurations using a variety of topologies as starting points. The amplifier synthesis module similarly eases the design of linear low-noise RF amplifiers.

Pete Johnson, director of marketing for xPedion Design Systems Inc., sees RF IC integration as a driver for much of his business too. Johnson said xPedion does not compete with Agilent EEsof EDA in traditional microwave markets. But working in RF CMOS and SiGe, designers need to worry about the leakage currents and noise that come with low-voltage operation. They typically overdesign to ensure working silicon at first pass, Johnson said, compensating for lower transistor performance, but using six to 10,000 of them for a single transceiver.

And the quality of the models for RF CMOS devices "is not all that great," Johnson said. Part of it is a foundry issue, he speculated. But this could mean an RF chip might have five or six spins before the designer has something that works. And although devices could appear to be working, there may be a problem with low yieldsalways more risky when using a newer technology.

To facilitate "best practices" for RF design methodology, Johnson said, harmonic-balance simulation, for example, should be complemented with time-domain analysis done on simulators like Cadence's Spectre RF. "You're looking to verify the operation of the entire radio," he said.

It is also desirable to conduct full-chip Monte Carlo simulation. "If you save a few percentage points on yieldthat's millions of dollars in high-volume production," Johnson said. Extracted views from a time-domain simulator enable engineers to visualize the parasitics in a circuit. "But in the RF space," Johnson said, "radios are so sensitive, you just can't tape out a chip with only fast SPICE."

- Stephan Ohr

EE Times

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