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Sony, Toshiba tip DRAM prototype

Posted: 01 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:sony? Toshiba? embedded-dram? cmos technology? soc?

Sony Corp. and Toshiba Corp. have jointly developed an embedded-DRAM cell measuring 0.069?m in 45nm CMOS technology. The companies presented their on-chip memory for high-performance SoC devices at the 2005 VLSI Symposia recently.

Sony and Toshiba are now in the third phase of collaboration, having jointly developed 90nm and 65nm process technologies. They have been collaborating on 45nm process technology since February 2004.

When the embedded-DRAM scales down, the capacitance of the deep-trench capacitor decreases. To compensate for that decrease, the R&D team introduced a bottle-etching process combined with a structure called a Locos collar, which enables the trench to form a bottle-like shape. Hence, the trench is wide, but has a narrow mouth. This shape increases the surface area of the deep trench, resulting in larger capacitance.

In addition to the trench's bottle-like shape, the companies used a high-k-node dielectric material (Al2O3) in place of conventional nitride-oxide insulation.

The DRAM prototype's data retention characteristicsthe key index of DRAM performanceare almost at the same level as that of 65nm embedded DRAM, the team said.

To improve performance and establish full compatibility with the logic process, a hybrid shallow-trench-isolation structure and a new strap structure have also been introduced to the embedded DRAM.

In a functional test of a 256Kb embedded-DRAM macro, a yield rate of 61 percent was obtained, the team reported.

The companies have spent a total of about $183.4 million to develop the process. About 150 engineers from both companies plan to gather at Toshiba's R&D center and Oita fab in March 2007 to establish the key technologies for the 45nm generation.

- Yoshiko Hara

EE Times





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