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PLD vendor releases open IP core soft MCU

Posted: 03 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:lattice? ip core license? ip? microcontroller? mcu?

PLD vendor releases open IP core soft MCU

In a move to drive user development of its new 8-bit soft microcontroller core, Lattice Corp. is offering an open IP core license that eliminates the boundaries found in free reference designs that restricts the use of IP.

Lattice's 8-bit soft microcontroller (MCU) core, LatticeMico8, is available for Lattice ECP, LatticeEC and LatticeXP families of FPGAs as well as the recently released MachXO family of crossover PLDs.

The IP core license applies many of the concepts of the open source movement of IP cores targeted for programmable logic applications. The license agreement addresses issues related to PLD-based designs, and allows designers to modify the core and share their changes.

"The most significant advantage of the Open IP license is that it encourages open community review and development of the Mico8 and associated tools. This ultimately should result in a higher performance and more powerful microcontroller. Customers also will find the flexibility of targeting the Mico8 to any architecture of their choice a significant advantage," said Gordon Hands, strategic marketing manager, Lattice.

Lattice typically has offered IP under two business models-fee-based and free reference designs. The models have been industry-standard methods used by all large PLD vendors when providing IP, Hands said.

"The Open Intellectual Property license removes the restrictions found in free reference designs that limit the use of the IP to a specific vendor's device, which makes life difficult for users who will do initial prototyping in FPGAs but then switch to ASICs, and the publishing of derivative works based on the reference design."

The LatticeMico8 microcontroller consumes less than 200 Look Up Tables (LUTs) in the smallest configuration. It also features 18-bit wide instructions, two cycles per instruction, 32 general purpose registers, and I/O performed using up to 256 ports. The user is offered 32 bytes of internal scratch pad memory, as well as the option of 256 bytes of external scratch pad RAM. The LatticeMico8 also features the company's UART reference design peripheral.

The Lattice Mico8 is optimized for Lattice architectures; however, a user doesn't have to be a Lattice PLD customer to use this, Hands said.

"We wanted to minimize restrictions on the use of this IP to maximize the opportunity for open community development of this IP," he added. "The Mico8 costs nothing to license. More importantly, unlike previous free reference designs, customers can target Mico8 to any silicon architecture (FPGA or otherwise), and develop and publish derivative works."

Core design is performed in Verilog, and an assembler and instruction set simulator is also provided as source code. A demo of the LatticeMico8 is available for download, allowing designers to work up a design in less than 30 minutes on an evaluation board.

The LatticeMico8 reference design, which includes the core, user guide, all tools and demo examples, is available now for immediate download at no charge on the company's website.

- Ismini Scouras


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