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Timing analyzer puts ASIC-like functionality in FPGAs

Posted: 16 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:actel? timing analysis? libero? integrated design environment? ide?

Claiming new functionality along with ease of use, Actel Corp. recently rolled out a static timing analysis engine as part of the Libero 6.2 integrated design environment (IDE) for Actel fpgas. The release also strengthens third-party tool support.

Libero 6.2 features smarttime, a new static timing analysis engine that replaces Actel's previous capability. Features include new timing analysis and constraint editor "views," visual constraint dialogs, clock domain management, enhanced Synopsys Design Constraint (SDC) support and "smart filters" to identify paths of interest.

"What we're trying to do is bring the kind of powerful functionality that is very present in the ASIC world into the FPGA world," said Michael Mertz, senior product marketing manager at Actel. With SmartTime, he said, ASIC designers will see concepts presented in a familiar way and FPGA designers will have a GUI that lets them learn concepts quickly.

Actel is also adding Mentor Graphics' ModelSim AE simulator to the free version of Libero for the first time and providing new releases of Synplicity's FPGA synthesis tool and Magma Design Automation's Palace physical synthesis tool as part of Libero 6.2. The new release also improves physical design.

SmartTime doesn't support the entire SDC format, but accepts a "significant subset," Mertz said. Constraints such as clocks, input arrival times and required output times can be passed to SmartTime in an SDC file. These constraints can be edited or created directly using SmartTime's constraint editor.

A new timing analysis view lets users read in their constraints and apply them to the design. Users have the ability to find the minimum cycle time for the design, identify all paths with timing violations and analyze delays of paths that have no timing constraints.

The timing analysis view also provides a "clock domain browser" that makes it possible to identify clock domains in the design and perform detailed analysis on paths that have sequential elements driven by different clocks. Users can cross-probe between the constraint editor and the timing analysis view.

Visual constraint dialogs let users edit their timing requirements and timing exceptions. These pop-up dialogs guide users by displaying the constraint information graphically and are linked to the timing analysis view.

What Actel calls smart filters provide a way to zero in on a particular set of paths. For instance, a user might want to look at all the paths that are going from inputs having "_4" in the name to all pins with "11" in the name.

While SmartTime was developed by Actel, Libero relies on third-party tools for the design implementation phase. New with the Libero 6.2 release, said Mertz, is Synplicity's Synplify 8.1a synthesis tool, which adds critical path resynthesis capabilities for Actel Axcelerator devices. Further, he said, Magma's Palace now supports Actel's Axcelerator family for the first time.

Physical design improvements include automatic local clock assignment, which performs automatic placement on as many as 18 local clocks, and incremental routing, which can process engineering change orders without redoing the entire chip.

Actel Libero 6.2 is available now. The free Gold version is limited to small Actel devices. Paid Windows and Unix versions provide access to all devices and are available for $2,495 and $4,995, respectively.

- Richard Goering

EE Times




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