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Build a differential circuit for OC-18 clock- and data-recovery

Posted: 15 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:1? 310nm? 850nm? multimode fiber? amplitude modulation?

By Mingliang Liu

At a specific characteristic wavelength (such as 1,310nm for a single-mode fiber, or 850nm for a multimode fiber), there are three main types of modulation schemes for modern fiber-optic transmission: Amplitude Modulation (AM, also known as Intensity Modulation); Frequency Modulation (FM), and Digital Modulation (DM). Each scheme carries some tradeoffs.

To understand the three schemes, consider the relationship between the loss in light intensity (or optical loss) and the loss in signal power (signal loss). Intuitively speaking, because the transmission medium is light in a fiber-optic cable, the optical loss will directly effect the signal integrity, which is normally presented as signal-to-noise-distortion-ratio (SNDR). Although ideally light can travel up to infinite distance in a vacuum field with zero gravity, in practice, light is subject to intensity loss over distance due to non-ideal effects in the cable. Some practical examples are light absorption by the glass surface, reflection by the cladding layer, and intensity loss due to water ions inside the fiber (called water peak). However, the sensitivity of signal loss to optical loss varies from one modulation to another (Figure 1). The AM curve's slope indicates that the SNDR drops about 2dB for every 1dB increase in the optical loss. This is a significant drawback of the AM scheme.

An FM signal is more robust with respect to optical loss compared to AM, but worse than DM. Within the practically usable optical loss range (around 0 to 10dB) for audio/video transmission, the FM curve indicates a lower SNDR compared to DM due to the modulation loss in centering the original base-band spectral to a high-frequency carrier, as well as the harmonics introduced by the pulse-frequency modulation. However, in a worse scenario where the optical loss is about to reach 20dB, FM demonstrates a better robustness than DM, whose SNDR curve drops sharply around the optical loss limit. Nevertheless, within the practical optical loss range from 0 to 10dB, DM is a better choice over FM, especially when the bandwidth requirement is stringent.

A key element in a digital fiber transmission system or a fiber transceiver adopting the DM is the integrated clock and data recovery (CDR) circuitry. The data stream transmitted over the fiber network is usually in the non-return-to-zero (NRZ) format. Also, its spectrum often contains no spectral components at the data clock frequency.

Figure 1: Shown are the SNDR vs. optical loss curves resulting from three modulation schemes

Filter- and phase-locked-loop-based CDR techniques have been widely used to extract the clock information from the NRZ data sequence. The filter-based architecture requires a precious and speed-limiting phase aligner due to its susceptibility to temperature and component variations. In addition, a high selectivity band-pass filter tuned at the clock frequency is required for jitter reduction. In contrast, the PLL-based architecture doesn't require accurate phase alignment thanks to its automatic synchronization characteristic1. A few CMOS PLL-based CDRs working at the speed comparable to the maximum operating rate of a digital latch have been reported2, which make them attractive for fiber-optical transceiver applications above 10Gbps.

Current-controlled oscillator
A ring oscillator with an even number of stages is a useful element of the CDR as it provides outputs with quadrature phase. The oscillation frequency is inversely proportional to the number of stages (N). Therefore, it's advantageous to decrease N for higher speed and less power consumption. However, the smaller the N, the higher the requirement for phase shift from each stage (180/N).

Our example design targets a minimum even-stage CCO, such as a two-stage CCO, for optimum speed and power (Figure 2). A working two-stage CCO requires a 90 hase shift from each stage1. A conventional differential stage composed of an inverter normally can't provide sufficient phase shift and gain. A double differential amplifier (DDA) has a symmetrical topology with a differential gain twice that of a conventional differential amp. The 360 overall phase shift around the loop is therefore provided by the two stages, and by the cross-wiring between the two stages, which inverts the overall dc phase and thus contributes the remaining 180 shift. The tail current Ictrl controls the delay per stage and thus the oscillation frequency.

Figure 2: The two-stage CCO circuit

The sizes and the bias of the PMOS transistors are chosen to generate a dc output voltage of about 2.2V on node y and y'. The conventional differential delay stage has no pole or zero near the center frequency (933MHz), where it shows a 90 phase shift (Figure 3). Both circuits have similar transistor sizes and biasing conditions.

The most significant difference between these two amplifiers is that the unbalanced PMOS current-mirror loads in DDA will cause a mid-band pole followed by an LHP zero. The conventional amplifier doesn't have this extra pole-zero pair because there's no signal passing through the mirror load (i.e., the mirror is a pure biasing). This configuration of DDA results in an extra negative phase drag around the center frequency and provide an excess phase shift, which can also be described as a phase backup (Figure 3, again). This featureis useful in compensating the phase shift's sensitivity to component and temperature variables. And it helps ensure that the two stages provide sufficient forward-path phase shift (180 in total) for stable oscillation3.

Figure 3: The three circuits show the frequency response comparison between a conventional amplifier and a DDA

It's also observed through measurement that DDA has a low-frequency gain that's 6dB larger than its counterpart. The phase comparison shows that the mid-band pole-zero pair isn't exactly one octave apart, and as a result, the largest phase shift is likely to occur at a frequency of about 1GHz. This isn't a problem to the overall design because the excess phase shift gain near the center frequency is about -20, which is adequate in most applications with throughputs below 10Gbps. Both the conventional amplifier and the DDA have a dominant pole around 42MHz and a RHP zero at about 33GHz. The DDA has a mid-band pole at 670MHz, followed by a LHP zero at 1.33GHz. The resultant CCO has a frequency to voltage gain of 235MHz/V. The measured phase noise performance show -93.8dBc/Hz at 100kHz and -109.4dBc/Hz at 600kHz.

Voltage-to-current converter
The V-I converter consists of two differential pairs in series. The dynamic range of linear operation is effectively doubled as the differential input voltage is divided among gate-sources of four transistors.

Looking at how the M5 transistor functions, when M6 is off, M6's the drain voltage, Vd6, equals Vdd. As a result, the gate voltage for M12, Vg12, equals VddVgs5 instead of zero (in the case when M5 doesn't exist). Therefore, Vsg12 equals Vgs5 when M6 is off. This gives a constant current through M12, which can be adjusted to equal the tail current by manipulating the current source connected to M5, I5, and the width of the M5 transistor.

The CMFB is a self-biasing circuit consisting of p- and n-type subcircuits. Assuming the current's value current through two subcircuits, the ratio of PMOS to NMOS size could be calculated using a basic MOS current equation to achieve the CMFB voltage at Vdd/2, which is equal to 1.65 V in this case.

Charge pump and loop-filter block
The standard loop filter plays three important roles: stability issue (to keep VCO's control voltage from going unstable by suppressing the high-frequency components in Vcontrol); increasing the loop bandwidth; and jitter reduction. The components inside the charge pump and loop filter, R1, C1, and C2 are designed for a 300kHz loop bandwidth and a maximum phase margin of 60.

PFD block

A PFD based on the three-state structure described above has been designed (Figure 4). The delay cell and a XOR gate needed to provide an additional time constant as part of the pre-processing of the NRZ data are considered in the design.

Figure 4: This PFD is based on the three-state structure

The transient response shows the output fosc is 935MHz for a 933MHz input signal and it has successfully locked at this frequency. The outputs of the PD, PFD and FD are in the right direction, suggesting the logic of the PFD circuit is correct. The input signal is a 3.3V peak-to-peak sinusoidal signal with a 933MHz frequency.

1 B. Razavi, ed. Monilithic Phased-Locked Loops and Clock Recovery Circuits, Piscataway, NJ: IEEE Press, 1996.

2 J. Savoj and B. Razavi, "A 10Gbps CMOS clock and data recovery circuit," Digest of Symposium on VLSI Circuits, pp. 136-139, June 2000.

3 H. Djahanshahi and C. T. Salama, "Differential CMOS circuits for 622MHz/933MHz clock and data recovery applications," IEEE JSSC, vol. 35, pp. 847-855, June 2000.

4 A. Pottbacker et al., "A Si bipolar phase and frequency detector IC for clock extraction up to 8Gbps," IEEE JSSC, vol. 27, pp. 1747-1751, December 1992.

About the author
Mingliang Liu
holds a BSEE degree from the Beijing Institute of Technology and an MSEE degree from Oregon State University. He served as a product development manager at Extron Electronics. Mingliang can be reached at

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