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Integrated PCI Express solution reduces third-party IP vendor risk

Posted: 17 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:pci express? pcie? rambus? pci-sig?

The loud cry of developers demanding a PCI Express (PCIe) solution that eliminates interoperability risk and complexities related to multiple IP vendors has been heard by Rambus Inc.

The company has delivered a fully integrated solution that allows optimization for a variety of applications. It has completed PCI-SIG compliance and interoperability testing, and meets the PCIe 1.1 base specification.

These attributes are key for customers, especially smaller companies that have had a tough time developing PCIe-based products by having to get different intellectual property (IP) blocks from different vendors, perform evaluation, integrate them, and test them for interoperability, according to Prakash Bare, general manager of Rambus' digital IP business.

"The integration is already done and the interoperability-compliance certification is already done, and optimization is done knowing what the different pieces of the total PCIe solution are, so the customer is getting a significant value from that," Bare said.

Over the last several months, Rambus has been working on its family of integrated PCIe interface solutions, which include both the physical layer (PHY) that is process dependent, and a digital controller, which is synthesizable and process-independent.

Design optimizations can be done across the PHY and logic layers, resulting in lower power, area and latency for cost- and performance-sensitive applications.

"The Rambus solution can be used in very high bandwidth, high lane count, up to 64 lanes, for network communications applications," said Julie Cates, senior product marketing manager at Rambus.

It can also be optimized for low latency for storage applications, as well as for low power and low footprint for consumer applications, she added.

Traditionally, Rambus has offered physical layer solutions for its memory interfaces and logic interfaces, such as Ethernet, PCIe, Fibre Channel, and network backplanes. The PHY needs to be hardened for a specific IC process. For PCIe interfaces, the company has been offering PHYs implemented in 180nm to 65nm processes from the leading foundries, such as Taiwan Semiconductor Mfg Co. and UMC Corp., as well as ASIC providers, she said.

"We have positioned ourselves as the leader in the market for these serial link interface solutions that address the Ethernet, PCIe and Fibre Channel markets," Cates said. "With the announcement that we made this week is getting the word out that we have a complete integrated solution that has the complete stack from the PHY to the MAC, the link and the translation layers."

Indeed, Rambus has been making some significant acquisitions over the last four years, but its latest one has given the company a very robust suite of PCIe digital controllers that include root complex, endpoint, switch point and multi-mode controllers.

Last April, Rambus acquired digital core IP and associated engineering teams from GDA Technologies, which has allowed Rambus to offer its customers complete, integrated interface solutions.

For PCIe, there are multiple types of digital controllers, depending on the application. Embedded processors or controllers use root complex digital controllers. Peripheral attachment subsystems use endpoint digital controllers. The PCIe specification also specifies switch point digital controllers.

"Rambus has been working very hard between the PHY team and digital controller team to integrate this solution and put in the hooks for further optimizing the solution for the applications," Cates said. "And we can demonstrate this."

Rambus is also offering an evaluation kit that supports electrical characterization; compliance and interoperability validation; performance evaluation and optimization; applications and software development; and thorough validation of target application.

- Ismini Scouras


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