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Telairity discusses H.264 processor at Hot Chips

Posted: 17 Aug 2005 ?? ?Print Version ?Bookmark and Share


Telairity Semiconductor Inc. has launched a microprocessor for high-definition video encoding at the Hot Chips 17 conference in Stanford, California, the company said.

The T1P2000 multicore video processor is the first processor design to implement the Telairity-1 architecture, which harnesses multiple independent vector/scalar cores and is designed to handle the H.264 (MPEG-4 Part 10) high definition codec, the company said.

"The best processor benchmark is the customer's application, and it is in this type of environment that we've designed and measured the capabilities of Telairity-1 to deliver the highest level of video processing available in a single chip," said Howard Sachs, founder, president and chief executive officer of Telairity Semiconductor (Santa Clara, Calif.), in a statement.

An H.264 compression engine requires 4 to 6 times the computational power of an MPEG-2 compression engine. The programmable Telairity-1 architecture delivers this power by combining five independent vector/scalar cores, a video controller, and a DRAM controller supporting an I/O bandwidth up to 5.3Gbits per second in a multicore SoC.

At a clock rate of 668.25MHz, or nine times the 74.25MHz 20bit video standard, the T1P2000 achieves a total sustained chip performance of 55.5 GOPS (Giga operations per second), Telairity said.

- Peter Clarke

EE Times

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