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Multicore CPU handles computational needs of HD video codec

Posted: 19 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:telairity-1? processor? telairity semiconductor? h.264? mpeg-4 part 10?

Using multiple independent vector/scalar cores and targeting high-definition video encoding, the multicore Telairity-1 processor from Telairity Semiconductor has been specifically designed to handle the demanding computational requirements of the H.264 (MPEG-4 Part 10) HD codec.

H.264 is set to supersede mpeg-2 as the standard by which HD video is compressed in the professional broadcast environment for transmission, storage, and editing, where the new standard will deliver the same or better picture quality with a lower bit rate.

Used at the heart of professional broadcast encoding solutions, the Telairity-1 T1P2000 will allow designers to build high-quality encoders with fewer chips at the board level, which translates into better reliability and lower production costs for OEMs. Where a general-purpose 600MHz to 1GHz DSP based real-time H.264 encoder implementation would require 18 to 32 DSPs and six or more FPGAs, the Telairity solution requires only four to eight Telairity video processor chips and one small FPGA to achieve equivalent bit rates.

H.264 encoding solutions implemented with Telairity-1 will offer the smallest footprint and lowest cost for broadcast-quality H.264 video compression, requiring typically less than one quarter the number of chips of general-purpose DSP solutions, claims Howard Sachs, founder, president, and CEO of Telairity Semiconductor. "Lower prices for HD equipment, ramping sales of HDTV receivers and monitors, and the availability of HD-DVD and Blu-Ray DVD players mean that HDTV has arrived. Now the industry is positioned to ensure that the reality of HDTV will live up to the audience's expectations. Encoders designed with Telairity-1 processors will play a major role in making this happen," said Sachs.

The programmable Telairity-1 architecture combines five independent vector/scalar cores, a video controller, and a DRAM controller supporting an I/O bandwidth up to 5.3Gbps in a single multicore SoC. Each vector/scalar core features four vector pipes with independent hardware, an independent scalar unit, 128KB of on-chip vector SRAM, a 4KB vector SRAM data cache, an 8-Kbyte scalar scratchpad memory, and a 32KB instruction cache. As a fully programmable chip, Telairity-1 will allow customers to modify or add new algorithms to customize or improve the encoder over time.

At a clock rate of 668.25MHz, or nine times the 74.25MHz 20-bit video standard, the T1P2000, first product implemented on the new architecture, achieves a total sustained chip performance of 55.5 GOP (Giga operations) per second.

"H.264 is an important new standard for HD broadcasting, and Telairity has positioned itself well with this architecture to take advantage of the demand for H.264 encoding equipment," said Michelle Abraham, principal analyst, Converging Markets & Technologies, Multimedia, at In-Stat.

Flexibility is another bottom-line benefit Telairity-1 delivers. Devices built on this architecture can be used for many different video-encoding applications, allowing OEMs to use the same platform to deliver a range of functional capabilities. Beyond professional broadcast applications, the Telairity-1 processor will be used to enable HD video applications in video conferencing, security and surveillance, and medical imaging systems.

Packaged in the 1156-pin FCBGA (flip chip ball grid array) package, samples of the first Telairity-1 product, the 668.25MHz T1P2000, are available now, with production quantities available in Q4 2005. Pricing in 10,000-piece quantities for U.S. delivery will start at $425.

- Marty Gold


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