Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Power/Alternative Energy
?
?
Power/Alternative Energy??

Ten steps to a low cost, high performance switcher to power your FPGA

Posted: 22 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:synchronous buck regulator circuit? switcher? fpga? national semiconductor?

By Wayne Rewinkel
National Semiconductor

Here's a simple synchronous buck regulator circuit (Figure 1) that can provide high performance at a very low cost. This switcher will operate from a 3.3V or 5V input rail, has an output adjustable from nearly zero to Vin, and can deliver several amps. It has high efficiency, is stable with small ceramic caps, can operate at 100 percent duty cycle, offers extremely fast transient response, has very low output ripple, and can have a sub-dime size footprint. Because of its cool operation and small footprint it can be placed near a low voltage load.

The circuit is based on a low cost hysteretic switching controller that was designed to drive a PFET in an asynchronous buck configuration. Synchronous operation is obtained by inserting Q2 in place of a catch diode and selecting Q1 and Q2 to have gate threshold voltages greater than one half of Vin. Synchronous switching means better efficiency at full load. This is especially true when Vout is relatively small compared to Vin since the NFET can have much lower loss than a diode. Lower light load efficiency is the tradeoff.

Chosing FETs with gate threshold voltages less than Vcc/2 should be avoided since this will result in a short period during each switching transition when both FETs are on causing a "shoot-through" current spike. Shoot through current spikes cause noise seen as high frequency ringing at the switch node, switching frequency glitches seen at every node, and increased switching loss.

Switching frequency is adjustable and predictable
The switching frequency, Fsw, of many hysteretic buck regulators is dependent upon the inductor ripple current and output capacitor ESR. Ripple current flowing through the ESR produces a ramping voltage at the loop comparator, FB, forcing a state change each time its threshold voltage is crossed. When relying on ESR, Fsw becomes difficult to control since ESR is a typical specification that varies with time and temperature. One can reduce this variability by using a ceramic capacitor with a separate small series resistor. This can be effective but hysteretic ripple will still be present at Vout and Fsw will still vary if any bypassing load capacitance is added. Ideally, one wants the switcher's output capacitance to have zero ESR to reduce switching noise and provide better transient response.


Figure 1: Simple synchronous buck regulator

The circuit of Figure 1 allows Cout to have zero ESR by using Rs, Cs, and Cff to inject ripple into the loop comparator. Then Fsw is dependent primarily on Vin, Rs, and Cff. Cout can be one or more 105F ceramic caps with typical ESR in the 3mO range less when in parallel. This ESR is low enough to be ignored so Fsw is determined from the values of Rs, Cff, the fixed 21mv hysteresis voltage of the LM3475, and loop delay time. Cs is just a coupling cap chosen large enough to provide low impedance at the switching frequency relative to Rs. Loop delay time is approximately 90ns for the LM3475 + 20ns for small FETs. Switching frequency can be approximated by:

Fsw = D*(1-D)*(Vin-Vout) / (Cff*Vhyst*Rs*(1-D)+Tdelay*(Vin-Vout)); where D = duty cycle, and Rs Note that the equation does not include L, Cout, ESRcout, or Iout.

Output voltage limits approach Vin and zero
The internal comparator at the FB pin trips when the voltage reaches 0.8V falling and (0.8V + Vhyst) rising so its center point is (0.8V + Vhyst/2). This leads to the following expression for Vout: Vout = (0.8+Vhyst/2)*(1+Rt/Rb)-Vg*Rt/Rb; where Vg = 0 for Vout >0.8V. In the rare instance where Vout must be set 0. A stable Vin can be used for Vg in some applications.

Required design inputs
One must provide these inputs(units) to begin a design:
Vin(V); input voltage in the 2.7V to 5.5V range,
Vout(V); desired output voltage, can be lower than Vref if Vg>Vref is supplied,
Vref(V); internal Vref of the device, 0.8V,
Vg(V); voltage supplied to the bottom of Rb, this is zero for VoutVhyst(V); hysteresis voltage from the device datasheet, 0.021V,
Tdelay(ns); prop delay from FB to Dr plus delay from Dr to the switch node, about 110ns,
Ioutmax(amp); maximum desired output current, Vripplemax(mv); maximum peak to peak output ripple voltage allowed,
Fsw(kHz); choose a switching frequencylower for efficiency and higher to reduce size. A circuit with low cost, small footprint, and good efficiency will have Fsw in the 200kHz to 800kHz range.

Ten steps to complete a design
The design process will have no iterations if part values are calculated in this order:

1) Q1-PFET and Q2-NFET, select parts with low RDSon and Vth>Vin/2

  • this is a chore that requires web time to find affordable parts that will work. Siliconix has several in SOT23-6 and 1206-6 packages with RDSon2.5V

2) L, select to limit peak-to-peak ripple current to about Ioutmax/3

  • Lmin(uh) = ((Vin-Vout)*Vout/Vin*3000/Fsw*1/Ioutmax)
  • peak current rating must be > 1.33*Ioutmax
  • select a part with low ESR for best efficiency, choose Lesr lower than RDSon in step1

3) D , the simple duty cycle approximation is Vout/Vin but a more accurate version is:

  • D = (Vout+Ioutmax*(esrL+RdsonN))/(Vin-Ioutmax*(RDSonP-RdsonN))

4) Cff, select a value in the 470pF-10nF range that makes Rs just under 100 kohm

  • Cff (nf)>((D*(1-D)*(Vin-Vout)/Fsw)-Tdelay*10^-6*(Vin-Vout))/(0.1*Vhyst*(1-D))

5) Rs, calculate the value and select the nearest 1 percent part

  • Rs(kohm) = ((D*(1-D)*(Vin-Vout)/Fsw)-Tdelay*10-6*(Vin-Vout))/(Cff*0.001*Vhyst*(1-D))

6) Rb, given Rs and Vout, select to form a 0.5V max signal swing at FB

  • Rb(k?) = (Vg-Vout)/(Vref-Vout)*Rs*0.5/(Vin-0.5)

7) Rt, given Rb, select to provide the correct Vout

  • Rt(kohm) = (Vref+Vhyst/2-Vout)/(Vg-Vref-Vhyst/2)*Rb

8) Cout, select based peak-to-peak output ripple voltage

  • calculate ripple current, Ippk = 1000*D*(Vin-Vout)/(L*Fsw)
  • Cout(uf) = (125,000*Ippk/(Fsw*Vripplemax), use 1 or more 105F/6V/X5R/0805 ceramic caps

9) Cs, select large enough to keep its voltage change small with respect to Vin

  • Cs = Cff

10) Cin, use 1 or more 10uf ceramic caps to limit ripple to 5*Vripplemax

  • Cin(uf) = 200,000*Ioutmax*D/(Fsw*Vripplemax)

A practical example design with test data
Figure 2 shows a dual implementation of Figure 1 providing 3.3V and 1.2V at 2A each based on the National LM3475 PFET controller and small Siliconix FETs. The LM3475 comes in a SOT23-5 package and the FETs in SOT23-6 packages.


Figure 2: Dual implementation of a synchronous buck regulator

The catch diode found in an asynchronous buck was replaced with an NFET, si3456bdv, for an efficiency improvement of 5 to 10 percent. Both FETs were selected for small footprint, low cost, and Vgs > Vcc/2. The Coilcraft DO1813HC.472 inductor was chosen based on its 2.6A rating, small footprint, and low cost. It is the highest loss element in each circuit buts its size and cost make it attractive. The MLCC caps chosen are 0805 size using X5R material since they tend to be very low cost. A single 10?F ceramic output capacitor provides less than 20mVppk output ripple. Reduced ripple can be obtained easily by paralleling two or more of these 10?F caps.

Figure 3 is a plot of efficiency and loss versus load current over a 0 to 2A range based on measurement data with Vin = 5V.


Figure 3: Efficiency and loss vs. load current

User tips
Higher load current capability and efficiency improvements can be obtained easily by selecting a lower loss inductor, paralleling FETs, or both. When using FETs with lower RDSon, shoot-through losses will cause increased bias current accompanied by noise. This problem can be controlled if each FET is turned off before the other is turned on. Figure 4 shows one way to do this. By adding a diode in parallel with a resistor, together in series with each gate, the resistor will increase turn-on time slightly while the parallel diode keeps turn-off time short. Rg values

Switching frequency and output voltage ripple can be affected by layout caused by leakage flux from the inductor crossing the FB trace. This problem can be minimized by keeping the FB trace short and using a shielded inductor. Internal soft start limits inrush current but since the LM3475 has no current limit of it own, it is best to use this circuit with an input source that is overload protected. If current limit is a "must have" and Vin is a 5V rail, the LM3475 can be replaced with a similar part that has a user adjustable current limit such as the LM3485MM.


Figure 4: Controlling bias current and noise

Summary
A hysteretic buck regulator circuit was presented along with a 10-step design procedure enabling the reader to quickly design a high performance switcher. Circuit attributes include unconditional stability, switching frequency max >1mHz, very low output ripple, very fast transient response, tiny footprint, and low cost. POL applications such as FPGA core or I/O power with voltage requirements ranging from 0.8V to 3.3V and load currents less than 5A, are well served.

About the author
Wayne Rewinkel
is a member of National Semiconductor's technical staff in the Chicago area. Wayne joined National in 1979 as an FAE and has held a variety of engineering and sales positions since then. He was a founder of National's Power Applications Design Center in Phoenix, where he designed hundreds of custom dc-dc converters. He began his career as a design engineer with Motorola in 1972 after receiving his BSEE from the University of Nebraska.




Article Comments - Ten steps to a low cost, high perfor...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top