Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Tensilica enhances methodology for 90nm design flow

Posted: 31 Aug 2005 ?? ?Print Version ?Bookmark and Share

Keywords:integrated circuit design? 90nm configurable processor? cadence design systems? synopsys?

Tensilica has enhanced its automated configurable processor design methodology to account for common IC design challenges with 90nm process technology.

Tensilica said the new enhancements, which support the latest capabilities of tools from Cadence Design Systems Inc. and Synopsys Inc., include automated generation of physical design flow scripts that significantly lower power consumption, automate the input of user-defined power structures and support crosstalk analysis.

"90nm design presents significant new challenges for IC designers," said Steve Roddy, Tensilica's vice president of marketing, in a statement. "By automating the script development for the best-in-class design tools, we can speed our customers' designs to market."

According to Tensilica, one of the big challenges presented by 90nm silicon is the dramatic rise in dynamic power consumption. Tensilica's solution is the insertion of fine-grain clock gating throughout the Xtensa LX core and all designer-defined extensions. Synopsys' Power Compiler is used for further power optimizations, Tensilica said.

Tensilica's enhanced methodology also includes automatically generated Xtensa layout scripts that automate the input of designer-defined power structure into the layout tools in order to help combat another 90nm design challenge and the increased severity of IR drop across power rails, the company said.

New automatically generated Xtensa layout scripts also automate electrical parameter input from tool-specific technology files to better model parasitic effects, according to Tensilica.

Separately Monday, Tensilica said that STMicroelectronics has achieved first silicon success on a chip which demonstrates that Tensilica's Xtensa V configurable processor achieves a clock rate of 500MHz at 90nm. Tensilica said ST's simulations on a second, forthcoming design using Tensilica's Xtensa LX processor, shows that Xtensa LX reaches 700MHz in 90nm technology.

- EE Times

Article Comments - Tensilica enhances methodology for 9...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top