Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Sub-$200 tools power 'farms' for verification

Posted: 01 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:aldec inc.? asic respin? simulator for networking applications? verification? verilog?

Stanley Hyduke sees a not-so-distant future for the semiconductor industry in which companies are running thousands of simultaneous simulations to cope with the verification bottleneck, even going so far as to conscript enterprise computers that typically go unused at night to help with the task.

Hyduke, president of Aldec Inc., believes that a paradigm shift is taking place within the industry. Even though companies are spending up to 70 percent of design time for verification on advanced designs, he said, there are still far too many ASIC respins and product cancellations due to poor design quality. That has led to a surge in testbench generation and, in turn, simulation time needed for verification, he said.

While simulation, especially on this scale, has traditionally posed a significant cost, Hyduke said that the combination of new inexpensive simulation tools and the availability of remarkably inexpensive computers from China are changing that.

Aldec's Riviera-SNA (simulator for networking applications) is an HDL simulator that is available in high-volume orders for less than $200 per seat. Aldec describes Riviera-SNA as a batch-mode, common-kernel, multilanguage simulator, based on the company's established vhdl and Verilog mixed-language simulation technology. Aldec said that it has included major gate and timing simulation-speed enhancements to Riviera-SNA to enable faster functional and timing design verification.

Aldec is already undertaking a massive installation of Riviera-SNA at an unnamed Japanese customer. The Japanese customer told Hyduke it got 10,000 computers from a Chinese manufacturer for $200 apiece, plus the cost of memory. The customer plans to use the computers to run simulations with Riviera-SNA, which goes for $180 per one-year license in quantities of 10,000. The combination will create a massive, relatively inexpensive verification farm that Hyduke believes can take the amount of design time spent on verification from 70 percent down to as low as 20 percent. Aldec believes that this installation will create the largest design verification server farm in the electronics industry.

"The market for Riviera-SNA is much larger than someone would expect," Hyduke said. "The demand for device quality is growing and the time-to-market window is getting shorter and shorter. People would pay $1 million or so to have it done in one-third or one-fifth of the time."

By contrast, Hyduke said, massive verification farms with 1,000 computers running 1,000 Riviera-SNA simulators could cost as little as $400,000 per year.

Riviera-SNA runs on the AMD Opteron 64 processor. The company expects to add support for Solaris 10 soon. Riviera-SNA handles VHDL, Verilog, SystemVerilog and SystemC mixed designs with support for PSL, OVA and SVA assertions.

In quantities of 1,000, the single-language version of Riviera-SNA is priced at less than $400 per one-year license. The mixed-language support is available at an additional cost, the company said.

- Dylan McGrath

EE Times

Article Comments - Sub-$200 tools power 'farms' for ver...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top