Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Engineers write up SystemC TLM concepts

Posted: 01 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:stmicroelectronics? soc? systemc? transaction-level modeling? abstract channel?

Claiming to document a major step forward in SoC design, STMicroelectronics (ST) engineers are writing a book about the SystemC transaction-level modeling that the European semiconductor giant uses.

Their book, Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems (Kluwer Academic Publishers), has seven chapters, each written by an ST engineer and edited by Frank Ghenassia. The book's concepts are supported by the transaction-level modeling (TLM) library standard released by the Open SystemC Initiative at the Design Automation Conference.

"We believe that we have found and delivered to the industry the next SoC design methodology breakthroughSystemC TLM," Phillippe Magarshack, ST's group VP of central R&D, writes in the book's foreword.

Early start

Magarshack calls SystemC TLM a "real paradigm shift" in the way hardware and software engineers work together at ST. It allows software development to start before the hardware architecture is frozen, he said, a concept that even extends to external SoC customers, who can start early application software development with a TLM-based SoC prototype platform.

In explaining TLM, the book's first chapter provides a brief overview and history. TLM models components as modules with a set of concurrent processes that calculate and represent their behavior. Models exchange communication as "transactions" through an abstract channel, separating communication from computation.

ST developed a bit-true, address-map-accurate, cycle-free TLM methodology based on events from the hardware/software system spec. Since early 2003, it has widely deployed transaction-level models for software development and reference models for functional verification.

The book describes three layers of abstraction in ST's new design flow: an SoC functional view, which is an executable spec comprising algorithmic software; an SoC architectural view, which provides the information needed to develop the software of a given SoC; and an SoC microarchitectural view, which includes the information for timed and cycle-accurate simulations.

Chapter two describes the value of TLM, which allows simulation 1,000x faster than rtl or cycle-accurate modeling and 10x faster modeling.

A subsequent chapter details TLM techniques, such as how to model APIs, create "initiators" that implement processes, create "target modules" that take charge of IP behavior and model interconnect.

A chapter on embedded software shows how TLM platforms support coding, testing, integration and validation. It describes the development of device drivers, TLM-oriented operating systems and firmware and TLM-oriented applications software.

A final chapter explains how TLM has been integrated into ST's design flow, both by extending the Spirit XML packaging standard to support TLM, and by developing the tools needed to integrate TLM into the flow.

- Richard Goering

EE Times

Article Comments - Engineers write up SystemC TLM conce...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top