Road map rethinks process reductions

For Paolo Gargini, the Intel Corp. manager who chairs the effort to define the International Technology Roadmap for Semiconductors (ITRS), nodes are out—cycles are in. If the road map committee has its way, individual chip-manufacturing process nodes will soon be relegated to the industry's scrap heap, alongside megahertz ratings for microprocessors and other outmoded metrics.

At a recent meeting to consider a draft 2005 edition of the ITRS, which serves as the semiconductor industry's technology development bible, the committee instead outlined "cycles" for DRAM, flash and logic chips. The draft defines a cycle as a shrinking of the half-pitch of metal lines by 0.5x every two cycle periods, which is about 0.71 times per cycle. Historically, the half-pitch—the width of a patterned line and its adjacent space, divided by two—has represented the most advanced capabilities of lithography at any particular moment.

The change in thinking is designed to bring the road map's metrics in line with the realities of actual chip making. In essence, the ITRS committee is saying that big process steps will give way to incremental ones, a change that will have implications going forward. The full revision of the road map must be approved in December at an ITRS meeting planned for Seoul, South Korea.

The proposed 2005 ITRS forecasts a two-and-a-half year cycle for DRAM, moving to three years in 2010; a two-year cycle for flash memory, going to three years after 2006; and a three-year cycle for logic.

The ITRS has been trying to force-feed a single image on an industry that now has at least three distinct gating factors, Gargini said. DRAM makers seek to add density by shrinking the half-pitch of the first metal interconnect layer. Flash vendors push the half-pitch at the first polysilicon layer, since that defines how many bit cells they can link. And MPU companies seek to double the transistor density, even if that means pushing the die to a slightly larger size, Gargini said.

Moreover, the cycle for flash is expected to be faster than that for DRAMs. Risto Puhakka, president of VLSI Research Inc., said he doubts that flash scaling will slow as quickly as the ITRS committee believes. Market competition is intense and flash makers can afford to throw money at phase-shift masks and other reticle-enhancement techniques.

"Moore's Law is not a constant and at different times in the history of the industry, scaling has alternately moved faster and slower," Puhakka said. "The next period may see a slowing. But now, chipmakers see advantages to increasing the functions per chip, which in some cases, means increasing the die size slightly."

Started in 1992, when the Semiconductor Industry Association (SIA) formalized the process, the ITRS has laid out the technical challenges to scaling and marked the dates when several companies reached a certain half-pitch, as measured by volume shipments of DRAMs—the most aggressive devices to shrink the half-pitch at that time.

That formula served well for a number of years. But the last few years have been totally confusing for the road map, said Bob Doering, one of two SIA representatives to the ITRS committee.

Marketers have distorted the node concept, which holds that a new technology generation should be measured by the lithographically-defined half-pitch. Companies might say they had a 90nm process, for example, if the half-pitch was 120nm and the gate length 60nm. In their defense, companies claimed consistency, pointing out that the 90nm process was a 0.7x linear shrink of whatever they had accomplished at the previous node. In one famous case, Sony Corp. claimed a couple of years ago that a key chip in its Playstation game console was a 90nm device; it was actually implemented in a 130nm process, according to Semiconductor Insights, a Canadian technology and patent-analysis company.

Doering, a technology strategy manager at Texas Instruments Inc., said it was in the spring of 1999, at a meeting in Munich, Germany, that frustrated ITRS committee members began saying the whole idea of nodes was getting too confusing and might be more trouble than it was worth. Just what, for example, is a 65nm process? "From where we sit, doing reticle inspection, we get to see a lot of different processes. And I can tell you that at 65nm, there are some processes that don't look at all like 65nm on the reticle," said Rick Wallace, executive VP at equipment maker KLA Tencor Corp.

Also, nodes have become more porous than in the past. "We see a lot of changes to processes at mid-node now," Wallace said. "There are a lot of 90nm speedups going on, for instance."

Moreover, there may not be any single process that is more or less the same throughout the industry. "The time is over when a process node came out with just one CMOS process that pretty much everybody used," said Ludo Deferm, VP of business development at the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium. "By 45nm, you will have to alter the process design to meet the requirements of the applications you think are most important. TI's process won't look like Intel's. A company that focuses on high performance won't have a process similar to a company that emphasizes low energy consumption."

These changes have profound implications that go far beyond how nodes or cycles are expressed. IMEC's Deferm warned that this new reality would be particularly problematic for foundries.

"In principle, they don't know what their customers' applications are ahead of time," he said. "You may see foundries having to develop a suite of different technologies at a single node—a silicon-on-insulator process, a multigate transistor, a high-k/metal-gate process—all for different end markets. These can't be modularized so that they are all options of one base process. They are different."

Advanced Micro Devices Inc. may already be adopting a cycle-based approach to incrementally adjust its wafer process. Its automated process management software uses five integrated algorithmic analysis systems to automate decision making so as to produce wafers with predictably consistent yields. Hence, AMD claims it can make adjustments as small as 1nm to the critical dimension of each wafer, thus incrementally moving to tighter processes in smaller steps—from 90nm to 80nm to 65nm, for example.

"We were impressed at the consistency of wafer yields from AMD's process, and we decided to license a portion of APM to apply to our foundry operation," Kevin Meyer, VP of worldwide marketing at Chartered Semiconductor, said recently at the Semicon West show. Chartered is an alternate manufacturing fab for the AMD64 microprocessors.

The ITRS 2005 edition could still be amended if suggestions come from the estimated 1,000 people worldwide who participate in the definition process. For example, Intel's Gargini said the 450mm wafer diameter is moving into the discussion phase. About 80 people participated in the debate about the next-generation wafer size and Gargini expects more discussions in the coming months.

On another front, the ITRS 2005 edition draft document says that high-k gate oxides will not be introduced until 2008, for high-performance and low-power chips. Bringing in a high-k dielectric—long the industry's holy grail—appears as elusive as ever, according to Doering.

The lithography section of the road map is getting cleaned up a lot, said Scott Hector, a Freescale Semiconductor Inc. technologist who heads ITRS' U.S. lithography working group. For one thing, the 157nm lithography generation, including immersion, was dropped from the road map, acknowledging the fact that wet 193nm lithography obviated any need for 157nm tools.

Also, the road map gives 193nm immersion more prominence for the 45nm half-pitch and acknowledges that maskless lithography and imprint lithography might have an impact four or five years from now. EUV lithography is expected to see the light of day around 2010 for 45nm half-pitches, but immersion lithography with higher-index fluids are also a possibility then.

- David Lammers

EE Times

Additional reporting by Ron Wilson and Nicolas Mokhoff of EE Times.