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Leaky chips test designers' skills

Posted: 01 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:synopsys? power? zarlink semiconductor? system-level intellectual property? eda tool?

The growing popularity of battery-powered portable products and their demanding feature sets require designers to eat and sleep power consumption. That means considering new approaches, such as turning off parts of a chip that aren't mission-critical or dynamically scaling voltage to achieve "good enough" performance for the task at hand.

It sounds simple, but it will be a difficult slog for many. "Power has changed the whole equation. In the old days, it was all about timing closure, and there used to be an 18-month lag between the early adopters and the mainstream community," said Purnima Gauthrom, product marketing manager of power products at Synopsys Inc. "With power in the equation, it will take longer than 18 months for the mainstream guys to catch on."

To achieve longer battery life in portable products, the entire IC design chain must chip in. The process starts at the architectural level and filters all the way through every link in the chain, taking advantage of new system-level intellectual property (IP) and advanced EDA tools and process technology.

Yet for some companies, especially communications specialists, power management is nothing new. Zarlink Semiconductor Inc. makes ICs that go into implantable medical devices such as pacemakers, and that forces Steve Swift, chief of the company's Ultra Low-Power Communications group, to think on the nanoamp level!orders of magnitude lower than what you'd see in consumer electronics products. Zarlink did the RF transmitter and controller circuit for the camera-in-a-pill, which sends 2fps (300 x 300 pixels, 16bit resolution) over the course of its eight- to 12-hour journey through a patient's most intimate thoroughfares.

In 1968, the company designed the first IC to go into a pacemaker. Since then, Swift's designers have devised numerous means for squeezing every nanoamp out of a design. And they've had to do it the hard way. "Synthesis for low power is something that's just beginning to be in vogue in the digital domain," Swift said. "Multiple-domain clock gating was something that, until recently, would cause the synthesis tools to just gasp and fall over. We would have to manually partition the circuit and synthesize pieces, and then reconstruct it."

That process is slowly changing, and the reason is simple: "In one design, a customer told us that one-half of their power consumed on-chip comes from leakage. That's astonishing," said Genda Hu, VP at foundry Taiwan Semiconductor Manufacturing Co.

As more designs move to 90nm and 65nm technology, blowing half the power budget on leakage could be the norm. For the 90nm node, up to 50 percent of a chip's power consumption may come from leakage; at 65nm, it may climb to 80 percent. "When we move to 90nm, power management is no longer just for the niche players, or guys that are doing leading-edge design or chips for cellphones," said Mike McAweeney, VP of industry alliances at Cadence Design Systems Inc. "Now it includes almost every customer."

That said, battery-sensitive applications, such as mobile phones and hard-drive-based MP3 players, top the list, along with the new generation of video-enabled personal media players.

Companies such as Freescale Semiconductor Inc. and ARM Ltd were among the first to experiment with multiple innovative approaches to minimizing power consumption. Freescale, for instance, has recast its cellphone system-chips into what it calls the Mobile Extreme Convergence Architecture (MXC).

In essence, Freescale engineers tinkered with their longstanding approach to cellphone architecture from the vantage point of power, to see how things would look if they integrated a dedicated application processor onto the same silicon as the modem. With MXC, they created a modem with a single core!most modems today use two!by shoehorning all the properties required of a modem onto a StarCore DSP via advanced DSP hardware and software architectures.

Integrating the single-core modem and the application processor on a single die offers more opportunities to share resources that were previously duplicated in the system. For example, there are shared memories, and redundancy is reduced by minimizing the number of processors required. That, in turn, reduces the associated memory blocks and other overhead, such as support logic. The result is a more power-efficient design.

But it's not all in the architecture. Freescale also made changes at the chip level. To reduce standby current!which is dominated by leakage!the engineering team went beyond typical clock gating. They also tried power-gating separate components on the part, such as memory, reducing voltage when possible. And they applied substrate biasing. "The most important thing is that we are looking at a combination of techniques," said Christopher Chun, a power-management specialist in Freescale's wireless solutions division. "It's no longer a silver bullet of one technique or another that will get us to the low power we need."

For the past three or four years, IP provider ARM has been working with National Semiconductor Corp. at that higher level to manage consumption, considering both clock frequency and voltage as possibilities that should be used in concert to control power draw. Portable systems that implement the partners' Intelligent Energy Management (IEM) and PowerWise IP started to appear in products last year.

The key to managing dynamic power here lies in the software. It works closely with the OS to predict the workload of the processor, which allows it to reduce clock frequency and voltage levels to meet the good-enough performance goal. "Only by controlling the voltage do you reduce the draw on the battery. If you just reduce the frequency, you draw the same energy overall, but it's just spread over a greater time," said Richard Williams, an engineering manager for methodology implementation at ARM.

Take video playback on a personal media player as an example. Using information within the player's OS that describes the application's performance needs, ARM's IEM software and Intelligent Energy Controller hardware work together to predict the lowest acceptable processor performance level. That information is then fed to National's power-control system to enable adaptive voltage scaling sufficient to achieve the frame-by-frame deadlines for the video's optimum 30fps playback.

At the silicon design level, EDA vendors, chip-level IP providers and the foundries are tackling similar challenges. The EDA community finds itself pushed by wireless-chip designers, who have been manually doing things like partitioning voltage islands and inserting level shifters at the RTL before passing that information on to the physical level.

Automating these techniques is fairly complex, though, because they touch every tool in the flow!from RTL synthesis, design planning and physical synthesis to place-and-route, test and formal verification, static timing analysis and full-chip power analysis. But the necessity is clear. "Some of the major wireless guys' customers are pushing to have their chips run at 1GHz in a system, and they have to reduce their leakage by 1,000x. These are real numbers and they are that bad," said Gauthrom of Synopsys.

"Some of these complexities have already been automated," said Ed Wan, senior director of design service marketing for tsmc. "For example, Synopsys and Cadence tools can actually recognize the different power domains, automatically insert these level-shifter cells in there and reroute the wires to connect the cells together."

TSMC's Reference Flow 6.0, released in June, focuses on power management using such techniques. Supply voltages for each block can be changed dynamically for variable performance requirements, which means that the chip won't overperform or always assume the worst-case scenario.

To tackle leakage, TSMC is supporting power-gating technology based on a multithreshold (MT) CMOS design structure. By inserting MTCMOS high-Vt footers to shut down the circuits that are not operating, TSMC believes leakage may be reduced by 90 percent or more, depending on the implementation being used.

The new reference flow looks at switching, area, timing and leakage as an interrelated problem instead of separate ones. The result was a 47 percent reduction in standby power and a 38 percent reduction in dynamic power, TSMC said.

- Mike Clendenin

EE Times




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