SDRAM in PBGA offers 74% space savings, 51% I/O reduction

White Electronic Designs Corp. (WEDC) announced its 256MB (2Gb) Registered Double Data Rate (DDR) Synchronous DRAM high-speed CMOS memory. The SDRAM is organized as 32M x 72, and is packaged in a 16-by-25mm, 400mm?, 208 PBGA. According to WEDC, this package is designed for high-reliability applications.

Available in commercial, industrial and military temperature ranges, the SDRAM in PBGA promises a 74 percent space savings and a 51 percent I/O reduction versus TSOP. It also offers reduced package weight, reduced part count, glueless connection to PCI bridge/memory controller, and reduced trace lengths for lower parasitic capacitance.

The 2Gb SDRAM uses DDR architecture to achieve high-speed operation. DDR architecture accomplishes this speed improvement by utilizing both edges of the memory clock for sending and receiving data, the company explained. It features enhanced performance bus speeds of 200-, 250- and 266Mbps, four internal banks for concurrent operation, and data mask (DM) pins for masking write data (one per cycle). The module offers differential clock inputs (CK and CK#) with commands entered on each positive CK edge,

The DDR SDRAM PBGA, defined as part number W3E32M72SR-XSBX, is priced at $250 each in volumes of 1,000 pieces with a lead time of six to 10 weeks.