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ST shifts 128Mb NAND flash memory to 90nm process technology

Posted: 02 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:stmicroelectronics? st? nand flash device? nand128w3a2bn6e?

Produced in 90nm technologySTMicroelectronics (ST) announced that production of its 128Mb NAND flash devicethe NAND128W3A2BN6Ehas been transferred to 90nm process technology. This shrink to 90nm promises a reduction in both the cost and the power consumption of the memory chip. According to the company, the NAND128 is currently the only 128Mb flash memory on the market to be produced in 90nm technology.

The NAND128W3A2BN6E is a 3V product, housed in a TSOP package, intended for consumer applications. ST disclosed that other family members, the 256Mb and 512Mb, both in 3V and in 1.8V versions, will also be moved from 120nm to 90nm technology in the coming months.

The NAND128 provides ultra-fast data throughput and erase capability. The Address lines and Data Input/Output signals of all members of the family are multiplexed onto an 8-bit bus, reducing pin count and allowing the use of a modular NAND interface, which enables manufacturers to produce variations of systems that use higher (or lower) density devices without changing the footprint.

A software tool chain available from ST allows fast product development, and can help extend the useful life of the memory chip. Tools include Error Correction Code (ECC) software; Bad Block Management (BBM) to recognize and replace a block that fails an Erase or Program operation, by copying its data to a valid block; Wear Leveling algorithms to optimize the aging of the device by distributing Erase and Program operations among all the blocks; File System OS Native reference software; and hardware simulation models.

The memory is organized into 1,024 nominal 16KB blocks, each of which is divided into pages of 512 bytes, plus 16 spare bytes per page, that can be read and programmed by page. The spare bytes are typically used for Error Correction Codes, software flags or Bad Block identification. A Copy Back Program mode enables data stored in one page to be programmed directly into another without the need for external buffering, a feature typically used to move data if a Page Program operation fails due to a defective block. A Block Erase command is provided, with a block erase time of 2ms. Each block is specified for 100,000 Program and Erase cycles, and 10-year data retention.

In addition, the Flash memory has the 'Chip Enable Don't Care' feature, which promises to simplify the microcontroller interface and streamlines the use of NAND Flash in combination with other types of memory such as NOR Flash and SRAM. A unique device ID can be factory programmed, and a User Programmable Serial number supports increased security in the target application, added ST.

Offered in a Pb-free TSOP48 package, the NAND128W3A2BN6E is already available in volume orders, with pricing between the $4 to $4.5 range. This new product is characterized for the -40?C to 85?C temperature range.

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