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Cadence reduces design cycles using SensorDynamics

Posted: 02 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:sensordynamics? sensor interfaces? custom design platform? bcd6? virtuoso xl layout editor?

Cadence Design Systems Inc. announced that SensorDynamics, a supplier of integrated microsensors, deployed the Cadence Virtuoso custom design platform for its latest chip designed for intelligent sensor interfaces.

The Cadence technology brought SensorDynamics reduced design cycles and significant time savings. The chip was produced in STMicroelectronics' BCD6 process technology, achieving first-pass silicon.

With the use of Virtuoso XL Layout Editor and Virtuoso chip assembly router, SensorDynamics achieved significant time savings for analog top routing and analog assembly. In addition, the use of the VHDL-AMS verification environment helped identify and solve a number of design bugs, which SensorDynamics claims would not have been discovered with a traditional methodology.

With Virtuoso AMS Designer simulator for VHDL-AMS verification, SensorDynamics was able to run intensive tests currently not possible with other methodologies.

The Virtuoso platform is a comprehensive system that enables design teams to deliver silicon that meets all specifications, as well as their schedules. It includes a specification-driven environment, multi-mode simulation, accelerated layout, advanced silicon analysis, and a full-chip integration environment.





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