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Dual-gate transistor-based DRAM to sample by year's end

Posted: 08 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:elpida memory? sdram? ddr3? edj5304aase? edj5308aase?

Implements dual-gate transistor technologyAs 2006 approaches, Elpida Memory Inc. is getting ready to supply next-generation memory for computing applications such as notebooks, desktops and servers.

With its latest announcement of a 512Mb double-date rate (DDR) 3 SDRAM, the company is touting more speed for less power. Compared with DDR2 technology, the DDR3 architecture doubles the transfer rate of the device, which can operate at speeds up to 1,333Mbps.

Elpida also claims that its latest memory chip is the first to implement dual-gate transistor technology, which is typically used in high-speed processors.

"Elpida is the first DRAM vendor to use dual-gate transistor for DRAM product offered in volume," said Jun Kitano, director of technical marketing for Elpida Memory (USA). "Previously, there have only been prototype DRAM devices with dual-gate transistors just as technology development."

Typical DRAMs use conventional transistor gate technology, which worked well up to DDR2 generation devices, he said.

"Dual-gate transistors can improve the transistor performance by suppressing the leakage current even at lower voltages. This characteristic provides ideal performance for DDR3, which needs to realize higher-speed operation but with lower voltage than DDR2," he said.

Elpida's 512Mb DDR3 SDRAMs offer low-power consumption?1.5V compared with 1.8V operation of DDR2 SDRAM devices. The device will feature automatic calibration for the output buffer that will enable the device to control the system timing budget during variations in voltage and temperature.

Elpida is offering three versions of the device. The EDJ5304AASE is a 512Mb DDR3 SDRAM organized as 16,777,216 words 4 bits 8 banks; the EDJ5308AASE is a 512Mb DDR3 SDRAM organized as 8,388,608 words 8 bits 8 banks; and the EDJ5316AASE is a 512Mb DDR3 SDRAM organized as 4,194,304 words 16 bits 8 banks. Both the EDJ5304AASE and EDJ5308AASE are housed in 78-ball FBGA package, while the EDJ5316AASE is offered in 96-ball FBGA package.

The devices will be manufactured using 90nm process technology. Because the device will employ dual-gate transistor technology, they are harder to manufacture.

"DRAM process technology is, in general, a heavier heat-load process than other device such as processors. This is due to the additional fabrication process step for the memory cell capacitor," Kitano said. "A heavier heat-load process generally results in wider distribution variation in transistor performance and makes it harder to satisfy both high current drivability and low-leakage current."

Since the company has already established volume production at 90-nm, it will be able to churn out DDR3 SDRAM devices and serve the market as needed. It expects to ship samples by the end of this year, and production to commence in 2006 in accordance with market demand.

The crossover timeline between technologies, such as DDR2 and DDR3, in the PC and server sectors is mainly driven by the chipset platform. So far, there has been an increase in speed for the high-performance PC segment each year.

This year, the standard speed is 667MHz and expected to go to 800MHz in 2006, followed by 1,066MHz in 2007, according to Kitano. The DDR3 architecture is designed to address speeds at 800MHz and beyond, he said.

"The volume production crossover is generally about nine to 12 months behind the high-performance segment," he said.

Elpida also plans to develop higher density DDR3 products, such as 1Gb and 2Gb, but wouldn't divulge any other details.

The company also wouldn't comment on whether dual-gate transistor-based DRAMs will carry a premium.

The pricing schedule won't be available until Elpida begins sample shipments of the DDR3 device. Pricing will be determined based on the market conditions when the product samples at the end of the year, according to a spokesperson.

- Ismini Scouras
eeProductCenter




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