Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Memory/Storage
?
?
Memory/Storage??

How to interface DDR-II SRAMs with Stratix II devices

Posted: 08 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:Cypress?

By Anuj Chakrapani, Cypress Semiconductor

Programmable Logic DesignLine

Synchronous static RAM (SRAM) architectures are evolving to support the high-throughput requirements of communications, networking, and digital signal processing (DSP) systems. Previous Sync SRAM architectures such as Std Sync and NoBL SRAM were limited by bandwidth and could not cope with the high-throughput requirements of high-speed applications.

DDR-I and DDR-II SRAMs that are a part of the Quad Data Rate (QDR) SRAM family, however, are ideally suited for high-speed networking applications. They support higher memory bandwidth by providing more than two times the bandwidth of prior Sync SRAM architectures by accepting data transactions on both edges of the clock. This makes them an enticing technology for applications that require data transfer at very high speeds. This article describes how to implement a DDR-II SRAM memory device with a Stratix II FPGA, including detailed timing analysis.

DDR-II SRAM overview

The DDR-II SRAM has a synchronous interface and can perform two data writes or two data reads per clock cycle. The same bidirectional data bus is used for writing and reading from the SRAM. The device uses three pairs of clocks: Input Clocks K and Kn for latching in the input address, controls and data, optional output clocks C and Cn for output data, and source synchronous 'echo' clocks CQ and CQn that are edge aligned with the output data. Write and read operations to the DDR-II SRAM are burst-oriented and support burst lengths of two and four, so each read and write operation transfers either two or four data words (See Figure 1).

DDR-II SRAM devices use the 1.5V-HSTL or 1.8V-HSTL Class I/II I/O standard. However, it is recommended to use the 1.8V-HSTL Class I I/O standard for maximum performance in Stratix II devices.


Figure 1

DDR-II SRAM functionality

Burst-of-2 and burst-of-4 devices provide the same overall bandwidth at a given clock speed. This section describes the functionalities of burst-of-2 and burst-of-4 DDR-II SRAM devices. From this point forward, write data to the memory is denoted by D, while read data from the memory is denoted by Q.

Burst-of-2 DDR-II SRAM devices

Burst-of-2 DDR-II SRAM devices support two-word data transfers on all write and read transactions, requiring a relatively simple controller implementation.

The figures below illustrate write and read operations with the device operating in dual clock mode (i.e., optional C and Cn clocks used). If the device is used in dual clock mode, timing parameters would be with reference to C/Cn, while in single clock mode (i.e., C and Cn clocks not used), timing parameters would be with reference to K/Kn.


Figure 2

The size of the Address, Data-I/O buses depend on the memory device with which the FPGA interfaces. The BWSn signal (used to control byte-level operations) is low for the entire cycle of Figure 2.

Write Cycle On the rising edge of the K clock, the DDR-II SRAM device latches the control signals R/W and LD and the write address A2 (Cycle 6 of Figure 2). On the next rising edge of the K clock, the DDR-II SRAM device latches the lower data word (DA2) on DQ and on the subsequent rising edge of the Kn clock, the device latches the upper data word (DA2+1), thus completing a write cycle.

Read Cycle On the rising edge of the K clock, the DDR-II SRAM device latches the control signals R/W and LD and the read address A0 (Cycle 2 of Figure 2). After a one-and-a-half-clock-cycle latency, the rising edge of Cn clocks out the lower data word (QA0) of address A onto the DQ bus and the upper data word (QA0+1) on the next rising edge of the C signal, completing the read cycle.

Burst-of-4 DDR-II SRAM devices

Burst-of-4 DDR-II SRAM devices support four-word data transfers on all writes and reads, reducing address bus activity. However, the control circuitry needed to interface to burst-of-4 DDR-II SRAM devices is more complicated than control circuitry for burst-of-2 DDR-II SRAM devices.


Figure 3

Write Cycle The DDR-II SRAM device latches the control signals LD and R/W and the write address A2 (See Cycle 8 of Figure 3) on the rising edge of the K clock. On the following K clock rising edge, the DDR-II SRAM device latches the first data word (DA2) on DQ. On the next Kn clock rising edge, the second data word is latched (DA2+1). The third (DA2+2) and fourth (DA2+3) words are latched in on the subsequent K and Kn clock rising edges, respectively, completing a write cycle.

Read Cycle The DDR-II SRAM device latches the control signals LD and R/W and the read address A0 (Cycle 2 in Figure 3) on the rising edge of the K clock. After a one-and-a-half-clock-cycle latency, the rising edge of Cn clocks out the first data word (QA0) of address A0 onto the DQ bus. The next rising edge of C clocks out the second data word (QA0+1). The subsequent rising edges of Cn and C clock out the third (QA0+2) and fourth (QA0+3) words, respectively, completing a read cycle.

DDR-II SRAM interface signals

Table 1 shows the DDR-II SRAM interface pins (i.e., clock, control, address, and data signals) and how to connect them to Stratix II devices. When interfacing with one DDR-II SRAM device, it is recommended to use a single-clock scheme where the DDR-II SRAM device's C and Cn port is tied to VDD (Single Clock Mode)


Table 1

Clock signals

DDR-II SRAM devices have three pairs of clocks: Input clocks K and Kn Output clocks C and Cn Echo clocks CQ and CQn,

The positive input clock, K, is the logical complement of the negative input clock, Kn. Similarly, C and CQ are complements of Cn and CQn, respectively. The DDR-II SRAM device uses the K and Kn clocks for write accesses and the optional C and Cn clocks for read accesses, if used. CQ and CQn are the source synchronous output clocks from the DDR-II SRAM device to accompany the read data.

The number of loads that the K and Kn clocks drive affects the switching times of these outputs. When a controller drives a single DDR-II SRAM device, C and Cn are unnecessary because propagation delays from the controller to the DDR-II SRAM device and back are the same. To reduce the number of loads on the clock traces, DDR-II SRAM devices also have a single-clock mode, where the K and Kn clocks are used for both reads and writes. In this mode, the C and Cn clocks are tied to the supply voltage (VDD). The DDR-II SRAM device still uses CQ and CQn for the echo clock from the memory device to the Stratix II device.

The Stratix II device outputs the K and Kn clocks and the data, address, and command lines to the DDR-II SRAM device. For the controller to operate properly, the write data (D), address (A), and control signal (R/W, LD, BWSn) trace lengths and their propagation times should be approximately equal to the trace lengths of K and Kn clocks and their propagation times. If the propagation delays for K and Kn from the FPGA to the DDR-II SRAM device are equal to the delays on the address (A) signals, the signal skew effect on the write and read request operations is minimized. The delay matching between write data (D) and K/Kn clocks is achieved by using identical double date rate output circuits to generate the clock and write data inputs to the memory.

next page





Article Comments - How to interface DDR-II SRAMs with S...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top