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Samsung, TSMC tip breakthroughs at ISSM

Posted: 09 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:lithography? virtual metrology? international symposium on semiconductor manufacturing? dram? asic?

At next week's International Symposium on Semiconductor Manufacturing (ISSM), Samsung, Taiwan Semiconductor Mfg Corp. and other leading-edge chip makers are expected to disclose at least some of the secrets behind their respective semiconductor manufacturing efforts.

This includes a dynamic dispatching technique for lithography, virtual metrology and other technologies. The ISSM event will be held in San Jose from Sept. 13-15. Details about the conference can be seen here.

At the event, South Korea's Samsung Electronics Co. Ltd is expected to present a paper, entitled "Dynamic Photo Stepper Dispatching/Scheduling in Wafer Fabrication."

The technology involves two components in the lithography cell: a separate dispatching and scheduling component. The dispatcher decides the "best stepper" for a particular lot in IC production, while the scheduler recommends the required number of steppers for each layer, according to Samsung.

The technology is said to be one of Samsung's key enablers to boost throughputs and cycle times. "Samsung is getting a phenomenal 21-day average cycle time in its DRAM fabs," said Dan Hutcheson, president of VLSI Research Inc.

"This would be an amazing figure even for an ASIC fab. No one has ever done that in DRAMs without killing tool utilization, which is the most significant factor in controlling cost in a memory fab," Hutchenson said. "Getting cycle times down so low has enabled Samsung to keep its costs down, while being more responsive to the market. Figuring out how Samsung did this has got to be a top priority for every chip maker."

Also at ISSM, silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) is expected to present a paper on a new and innovative technology called virtual metrology. The paper, dubbed "Virtual Metrology: A Solution for Wafer to Wafer Advanced Process Control," describes a way to add virtual metrology between a tool and a lot APC controller in a fab.

Te technology is said to predict wafer performance in a foundry at levels of R2 > 0.97 with more than 500 wafers. "Virtual metrology is a novel technology to predict wafer performance from tool state variables," according to TSMC. "Virtual metrology can enable wafer to wafer control without additional real metrology."

To enable the technology, TSMC said that sensors can be installed on fab tools to monitor various conditions, such as temperature, power, flow rate, pressure, optical emission and plasma impedance. After a few wafers are measured from a lot in production, then virtual metrology will be deployed to estimate the process results of unmeasured wafers, according to TSMC.

Virtual metrology has been shown on both deposition and etch equipment, enabling higher throughputs, according to TSMC.

- Mark LaPedus

EE Times





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