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ST, Synopsys conduct testing of SATA IP cores for 90nm tech

Posted: 23 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:90nm? serial ata? multi-interface phy? designware sata? intellectual property?

STMicroelectronics and Synopsys Inc. are working together to conduct Serial ATA (SATA) interoperability testing using ST's 90nm MIPHY (multi-interface PHY) physical layer interface macro-cell and Synopsys' DesignWare SATA host controller intellectual property (IP) core. Interoperability testing reduces integration risk and speeds time-to-market for designers integrating SATA functionality into their system-on-chip (SoC) designs.

The joint STMicro and Synopsys solution for SATA is fully compliant with the current version of the SATA Integrated Specification Revision 2.5, including support for the latest features such as Native Command Queuing (NCQ) and 3Gbps (gigabits per second) operating speed. The MIPHY test chip already operates at up to 6Gbps, preparing the way for the next evolution of the SATA and SAS standards.

The DesignWare cores SATA Host controller is a high-quality, silicon-proven ip core designed for easy SoC integration. The IP uses the popular AHB standard for a host interface and configurable PHY/link interface to support a number of industry PHYs. Synopsys provides a large set of parameters to enable the IP's integration in systems with different requirements. By leveraging these parameters, designers can optimize gate count and reduce integration time.

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