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Forte upgrades Cynthesizer

Posted: 26 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:forte design systems? cynthesizer? behavioral synthesis? cynthesizer v2.5?

Forte Design Systems announced that it has upgraded its Cynthesizer behavioral synthesis solution to provide a more extensive production ESL design flow. Already available, the Cynthesizer v2.5 supports power estimation, formal verification, modular interface IP, FPGA prototyping, and a comprehensive design reporting subsystem. According to the company, these new capabilities give design teams early access to critical design information, ease the adoption of higher-level design, and further improve quality of results.

Through the company's collaboration with Sequence Design, Cynthesizer customers now have the ability to easily and automatically measure power consumption at the RTL and gate level using Sequence's PowerTheater product. By measuring power throughout the SystemC-to-netlist design process and reporting power estimates along with area and timing, users have the ability to tradeoff cost (area), performance and power to achieve the right mix of RTL quality for their target application.

Designing interface protocols is both time-consuming and error-prone, said Forte. With the latest release of Cynthesizer, design teams can easily incorporate modular and configurable interfaces with their C, C++ and SystemC design models, and create reusable interface IP. Cynthesizer automatically produces an RTL hardware description with an optimal schedule and resource utilization for the interface protocol being targeted. Customers can then perform "what-if" analysis for various interface options by changing the type declaration in their C code.

The upgraded version also includes support for RTL-to-gates formal verification with Cadence Design Systems' Encounter Conformal Equivalence Checker. Designers can now automatically verify the optimized RTL created by Cynthesizer with their post-logic synthesis netlist results, providing a more robust netlist sign-off flow. This capability allows design teams to quickly integrate Cynthesizer into their existing ASIC and SoC design flows, said Forte.

The company has also added support for FPGA implementation targets, eliminating the need for several different RTL design versions for multiple devices and reducing the overall design and verification effort. Cynthesizer users can now prototype their designs as FPGAs through a link with Synplicity's Synplify Pro, enabling fast RTL verification and early testing of new algorithms. They can later target an SoC/ASIC for high-volume production based on the same high-level SystemC model.

"With the growing adoption of Cynthesizer for production designs by major electronics companies, our customers are pushing the envelope with their demands for the critical functionality required both for broadening production use of ESL flows and for designing hardware at a higher level," said Brett Cline, Forte's VP of customer operations & services and corporate communications. "Forte has further extended Cynthesizer's existing technology lead by tackling issues such as power, IP reuse and formal verification, which will further improve quality of results and the applicability of ESL in production design flows."




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