Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Manufacturing/Packaging

Strained silicon to take IEDM spotlight

Posted: 27 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:45nm? metal gate electrodes? hybrid crystal?

With high-k dielectrics apparently delayed beyond the 45nm node, this year's International Electron Devices Meeting will focus on second-generation strained-silicon techniques as the main pathway to faster transistors. Technologists will also tout other new ways to boost transistor performance at IEDM, planned for Dec. 5-7 in Washington, including metal gate electrodes and hybrid crystal orientations.

Further, IEDM will put emerging technologies in the spotlight, such as Sony Corp.'s magnetoresistive memory, the Spin-RAM. The device employs the spin torque of electrons to achieve 2-nanosecond access times.

A few years ago, the industry thought high-k gate oxides would be ready for prime time by 2007, when early manufacturing would commence for transistors with a half-pitch of 65nm and gate lengths in the 30nm range (sometimes referred to as the 45-nm node). Then researchers realized that high-k oxides would require metal gate electrodes, ideally created by depositing two separate metals tuned to the N- and PMOS transistors. When the search for those metals proved difficult, the research community's attention turned to approaches that would transform doped polysilicon to a largely midgap metal through a silicidation process. Companies then realized that the metal gates could be used with nitrided silicon dioxide, rather than a high-k, to reduce polysilicon depletion.

At the 2005 IEDM, Intel Corp. researchers will describe a 45nm-node technology that includes fully silicided (FUSI) nickel electrodes. The FUSI-created metal is combined with the uniaxial strained-silicon channels that Intel first implemented at the 90nm node.

According to an abstract of the paper, the fully silicided electrodes improved charge density while the strained silicon enhanced the carrier mobility, a complementary effect that Intel said results in a 20 percent performance improvement over the conventional polysilicon gate electrodes used with nitrided silicon dioxide.

An Intel spokesman declined to say whether the company will adopt the FUSI electrodes for volume manufacturing. But the 20 percent drive current improvement cited in the abstract-1.75 microamperes/micron for the NFET devices, 1.06 mA/micron for PFETs-is the kind of performance boost that most companies expect as they shrink transistors from one node to another.

There appears to be a good chance that FUSI is, in fact, on Intel's process road map. As recently as mid-June, at the 2005 Symposium on VLSI Technology in Kyoto, Japan, the company said it had yet to find a high-k, deposited metal gate combination that met its criteria for the 45nm node, which goes into production in about two and a half years (see June 20, page 8).

IEDM also will hear AMD, IBM, Sony and Toshiba researchers, working at the IBM Semiconductor Research and Development Center at Hopewell Junction, N.Y., describe a process that uses several techniques to strain the silicon channels IBM and partners may have developed a commercially robust method of boosting performance with acceptable levels of additional complexity. Using its baseline 65nm process, which already includes dual nitride-induced stress liners, the Hopewell Junction team added additional sources of stress, including epitaxial silicon germanium grown in the source/drain areas of the PFETs, similar to Intel's strained-silicon approach. The team developed stress-memorization techniques in the NFETs, in which a nitride layer is placed on the gate before annealing the source/drain regions. These regions recrystallize during the anneal, introducing strain. When the nitride layer is removed following the anneal step, the strain remains.

The IBM team said it has also developed a low-k material that held up under the stress-inducing processes, enabling a significant reduction in wiring delays for the 65nm process.

Separately, a team from Toshiba Corp. will report on a 45nm-node process that incorporates two forms of strained silicon, combining dual stress liners with the deposited SiGe at the source and drain regions. Like the Intel and IBM advances, the Toshiba work avoids bringing in a high-k dielectric to the gate oxide, instead sticking with the tried-and-true nitride oxide (SiON).

Another Toshiba paper, from the company's Advanced LSI Technology Laboratory in Kawasaki, Japan, investigated a lanthanum aluminate oxide material with a k-value of about 25. The LAO films were fabricated with a high-temperature laser-sputtering method that resulted in no observable interfacial oxide between the high-k material and the silicon substrate, the laboratory said.

The LAO dielectric delivers an electrical oxide thickness of only 3 angstroms, equivalent to SiON, with gate leakage of just 0.1 A/cm2. However, the Toshiba researchers found that electron mobility was impaired by about 40 percent compared with SiON, though they speculated that mobility could be improved by optimizing the anneal process.

Hybrid surfaces

Another team of IBM researchers added hybrid-orientation silicon to the 65nm bulk silicon process, achieving 35 percent faster PFETs. The team's breakthrough was in directly bonding silicon with different orientations.

For several years, IBM has presented work on its hybrid-orientation technology at IEDM and other venues. That work, motivated by the long-understood fact that PFETs run faster in so-called 110 silicon, involved complex processes, starting with silicon-on-insulator (SOI) wafers and creating epitaxial silicon with a different crystal orientation. While the resulting combination of 100-oriented and 110-oriented silicon created fast CMOS devices, it was a multistep process to get there.

The team's Direct Silicon Bonding technique integrates bulk NFETs on 100 surfaces and bulk PFETs on 110-oriented silicon, using solid-phase epitaxy to convert the crystal orientation in the NFET regions from 110 to 100, according to the paper's abstract. By placing the NFETs on 100 surfaces and PFETs on 110 silicon, the direct-bonding method improves the ring oscillator performance by 20 percent, IBM said. Much of that advance is due to the PFETs, which ran 35 percent faster in the 110 silicon.

Looking further out, a team from Japan's government-backed Mirai-Aset research consortium will describe FinFETs made with SiGe-on-insulator, to which biaxial strain techniques have been applied. The structures are tall-nearly twice as high as they are wide-making it impractical to apply the same strain techniques that work so well in planar devices to the more-vertical multigate devices.

The Mirai team created PFETs that combined deposited SiGe, compressive uniaxial strain and 110-oriented silicon, obtaining additive enhancements from the combined boosters. The resulting FinFETs had 45 percent more on-current than comparable FinFETs created on conventional, unstrained SOI wafers, the group said.

The devices exhibited good resistance to short-channel effects, one of the strong points of the FinFET structures.

Sony's Spin-RAM

A session on emerging device concepts, planned for Dec. 6, will kick off with Sony's presentation of a prototype Spin-RAM that uses the spin torque of electrons to program a magnetic-tunnel junction (MTJ) with two ferromagnetic layers, separated by a spacer. The Sony researchers built a 4-kbit memory cell using a standard 180-nm CMOS process.

The cell, which is oval in shape, undergoes magnetization reversal through the interaction of a current created by the spin torque and the magnetic moment, or state, of the memory layers in the MTJ. No external magnetic field is required to program the MTJ, which under the right conditions results in sharply reduced power consumption compared with a conventional MRAM.

The paper's abstract describes a trade-off between the pulse width and the write threshold current. For write times of less than 10 ns, the switching current increased sharply, while for long pulses of 1 ms, the cell achieved a relatively low write threshold of 300 microamps-about one-twentieth that of a conventional MRAM. Work is needed to improve the spin torque transfer efficiency and the thermal stability of the magnetic layer, the Sony paper says.

A session on carbon nanotubes and nanowires includes a paper from Lund University in Sweden. The team there used chemical-beam epitaxy to create a vertical array of nanowires made of an indium-arsenide alloy. Taking advantage of the transport properties of indium, the Lund team created transistors with high mobilities through the nanowire-enhanced channel. With additional enhancement, Lund predicts, mobilities could reach 10,000 volt-seconds per square centimeter.

The Lund team grew the InAs nanowires with selective chemical-beam epitaxy at 440 degrees C, employing lithographically defined gold disks as catalysts during the wire creation process.

The 2005 IEDM includes 250 paper presentations over three days. One keynote speech, by Stanford University professor Mark Horowitz, will consider power limitations as CMOS scaling proceeds. Evening panel discussions will include one in which Intel Fellow Greg Atwood will lead a group of experts as they consider the prospects for emerging nonvolatile memories.

- David Lammers

EE Times

Article Comments - Strained silicon to take IEDM spotli...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top