Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

Renesas reports floating-body SOI RAM

Posted: 28 Sep 2005 ?? ?Print Version ?Bookmark and Share

Keywords:renesas technology? floating-body? twin-transistor ram? ttram? system-on-chip?

Renesas Technology Corp. said early this week that it has developed a capacitor-less "floating-body" twin-transistor RAM (TTRAM), that would enable faster, more power-efficient embedded memory for soc devices.

The TTRAM is intended to be used with 65nm generation and subsequent SOI CMOS manufacturing processes, Renesas said. It also has similarities to a floating-body, capacitor-less memory developed by Innovative Silicon Inc. of Santa Clara and Lausanne, Switzerland.

A 2Mb TTRAM test chip fabricated with a 130nm SOI CMOS process, achieved 250MHz operation for sustained data output and 133MHz for random access operation, while dissipating an active power of only 148mW. This is 43 percent less power consumption than a conventional embedded DRAM within Renesas 130nm CMOS process.

Researchers discussed the TTRAM in a paper presented at the IEEE Custom Integrated Circuits Conference (CICC) held in San Jose, California, last week, Renesas said.

As the TTRAM memory cell doesn't use a capacitor, it is compatible with process technology shrinks that make transistors smaller and faster and this provides roadmap for future manufacturing. The cell size on the 2Mb test chip is 0.33?m?, over five percent smaller than the cell size a 130nm CMOS embedded DRAM test chip, Renesas said.

In the TTRAM memory cell, two transistors are serially connected on an SOI substrate. One is an access transistor, while the other is used as a storage transistor and fulfils the same function as the capacitor in a conventional DRAM cell. Data reads and writes are performed according to the conduction state of the access transistor and the floating-body potential state of the storage transistor.

The use of a floating body in an SOI process also allows Innovative Silicon to dispense with the charge-storage capacitor at each bit node. Innovative Silicon has called its memory Z-RAM to indicate zero capacitor and is working with SOI process specialist Freescale Semiconductor Inc. Although at 1Mb it's own test chip is smaller than that of Renesas, it has been fabricated using a more finely drawn manufacturing process, a 90nm SOI CMOS. Innovative Silicon claims the Z-RAM can achieve five times the density of embedded SRAM and twice the density of embedded DRAM while using standard SOI logic processes.

- Peter Clarke

EE Times

Article Comments - Renesas reports floating-body SOI RA...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top