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Denali spreads new word in ESL mart

Posted: 03 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:denali software? esl? register description language? blueprint compiler? rtl?

Denali Software Inc., best known for its memory and verification intellectual property, is leaping into the electronic system-level (ESL) market with a missionary zealand a product it believes will establish a new industry-standard language and chip design methodology.

Denali's Blueprint product includes the Register Description Language (RDL), a high-level language used to describe control registers, and the Blueprint Compiler, which takes RDL and generates several different "views." These include synthesizable RTL for hardware design; systemc or hardware verification language models for verification; C code for software and firmware engineers, and documentation ready for formatting.

Denali representatives say Blueprint is pragmatic, easy to understand and meets an immediate need. "If the world tomorrow adopted RDL, and all IP blocks were delivered in RDL, thousands of engineering hours would be saved every year," said Mark Gogolewski, Denali's CTO.

Sean Smith, Denali's chief verification architect, noted that registers define the software and firmware interface to a device. By generating SystemC models and documentation, Blueprint makes it possible to generate IP and software much more quickly, he said. "This is a tool that brings together all the different pieces of executing a chip and a system," he said. "I think our audience is everybody."

It may take a while for that to happen, but Denali has clearly impressed Michael Uhler, CTO at MIPS Technologies Inc. While it's not in production use at MIPS yet, Uhler said he is "very enthusiastic" about Blueprint's prospects. "There are many registers involved in a design and each has a different view," said Uhler. "There's a hardware view, a verification view and a software view. The problem is that people are spending too much time describing the same hardware in different ways."

For years, Uhler said, "A lot of us thought that there should be some mechanism for creating a metadescription of these things and generating outputs. Almost everybody has some ad hoc solution, but Blueprint has the promise of almost being an industry-standard solution to this problem."

New tool category

Gary Smith, chief EDA analyst at Gartner Dataquest, said Blueprint fits into a new tool category called "ESL target compilers." Such compilers, he said, are a "natural fit" to complement IP blocks.

Blueprint, said Smith, "looks like a good product. It's good to see Denali continuing their technology growth. Too many EDA companies are standing still right now."

Denali did not, however, create Blueprint. The product comes from a customera systems design house that Denali declines to name. "This is the third generation of the technology from that systems house and they have used it on dozens of multimillion-gate designs," Gogolewski said.

The systems house, said Gogolewski, wanted to find a partner that could not only take Blueprint to market, but could also "embrace a road map for standardization" of RDL.

Blueprint may seem like a substantial departure from Denali's core business, but that's not really the case, said Sean Smith. "I really don't think we have been in a different market," he said. "Registers define the interface of software to a device and Denali is a longstanding provider of design and verification IP. There's a tremendous synergy."

It's easy for engineers to understand the need for the tool, Smith said. Today, he noted, control registers often define the largest part of a programming specification, consuming perhaps thousands of pages of documentation. Typically, design teams start with specifications in Framemaker or Word.

From these lengthy written descriptions, hardware engineers write verilog design" target=_blank>vhdl or Verilog code, verification engineers write Vera or "e" language models, and software and firmware engineers write C code. But then something changes and everyone starts the process all over again.

Blueprint's RDL solves that problem, Smith said, by providing a central point for the specification. "You don't have the quality problems of five different engineers creating five different views and keeping them all in sync," he said.

RDL, Smith said, is an object-oriented language that is "very good at doing simple things easily." Its syntax and semantics are similar to those of Verilog and C. RDL, however, works at a much higher level of abstraction than VHDL, Verilog or even SystemC, he said, adding, "We are working on a road map for standardization to drive this into the industry."

But RDL won't necessarily match the efficiency of hand-coded RTL. "Anytime we raise the abstraction level, there is some potential for trade-off," Smith said. "Clearly, someone could say, I've got one NAND gate less [with RTL], but that's the wrong way of looking at the problem. The problem is: How do you build a 50Mgate SoC and get it right the first time?"

Gogolewski said that register design needs to be commercialized and commoditized. "Registers are not the place in which to differentiate," he said.

In addition to synthesizable VHDL, Verilog or SystemVerilog, Blueprint generates assertions in the Open Verification Library format that define rules for the correct operation of each register. For verification, Blueprint outputs models of the registers that users can bring into SystemC, OpenVera, "e," Verilog and SystemVerilog models.

Blueprint includes C and C++ generators for software development. Finally, Blueprint outputs documentation that's compatible with user templates for Framemaker, Word, HTML, XML or RTF-based documentation.

Priced at $500,000 for an enterprise site license, Blueprint is not cheap. But that license can potentially support hundreds of users, Smith noted. "It's a very cheap price, given the productivity gains across software development, documentation development and RTL," he said.

- Richard Goering

EE Times




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