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New DFM reference design flow for austriamicro's CMOS process

Posted: 07 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:austriamicrosystems? austriamicro? design for manufacturing? dfm? reference design?

austriamicrosystems' business unit Full Service Foundry recently announced the availability of its DFM reference design flow for its 0.35?m high-voltage CMOS process. The DFM-enhanced reference design flow utilizes specific analog high-voltage DFM tools such as design and layout verification of circuit robustness, yield optimization, parasitic simulation or safe operating area check. The company also provides full design support, including analog high-voltage DFM guidelines and DFM design review as optional services to its foundry customers.

The high-voltage CMOS process (H35) is a new generation advanced analog and mixed-signal technology offering 20V and 50V HV MOS devices and very low 'on resistances'. Available in several process options, H35 is suitable for a variety of applications, including power management, motor control, printer head drivers, DC/DC converters, switched power supplies, LCD drivers and backlight controllers.

"Using our DFM reference design flow ensures optimization towards yield and robustness of analog high-voltage CMOS designs," said Peter Gasteiner, SVP and GM of austriamicro's business unit Full Service Foundry. "Offering DFM services gives us a clear competitive advantage and strengthens our position as a leading supplier of high-voltage CMOS silicon foundry services. Our customers benefit from improvements during project ramp up and reduced time-to-market."

The company's process design kit "HIT-Kit" fully integrates these DFM features and promises optimization towards yield and robustness of the design during the whole design process. It comes complete with fully silicon qualified standard cells, periphery cells and general purpose analog cells such as comparators, operational amplifiers, low power A/D and D/A converters. Custom analog and RF devices, physical verification rule sets for Assura and Calibre as well as excellent characterized circuit simulation models enable rapid design starts of complex high performance mixed-signal ICs, added austriamicro.

All I/O structures within the design kit are silicon-validated and meet the military ESD and JEDEC latch-up standards. In C35 technology, the total I/O libraries consist of more than 1,800 cells supporting 3.3V and 3.3V/5V designs. The high-voltage CMOS process H35 with its floating libraries includes more than 2,400 core and periphery cells.




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