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Software offers graph-based physical synthesis into FPGAs

Posted: 11 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:synplicity? fpga synthesis tool? synplify premier software?

Synplicity Inc. has expanded its Synplify family of FPGA synthesis tools with Synplify Premier software.

The backbone of the Synplify Premier software is a new graph-based physical synthesis technology, an automated, single-pass design flow that is designed to improve timing performance and timing correlation, as well as reduce design cycle time and iterations.

Using this graph-based approach to physical synthesis, designers are able to close on aggressive timing requirements much faster while achieving a performance improvement of up to 20 percent compared with logic synthesis alone, the company said.

"Synplicity was the first to deliver physical synthesis for FPGAs, and with our next-generation graph-based approach to physical synthesis, Synplicity continues its commitment to technology innovation," said Andy Haines, senior vice president of marketing at Synplicity, in a statement. "Better timing closure and physical optimizations all hinge on highly accurate timing estimations before running place and route. We believe our new graph-based physical synthesis technology delivers the accuracy needed to reduce design iterations and meet aggressive performance goals quickly and reliably."

Synplicity's new graph-based physical synthesis technology creates a detailed routing resource graph of pre-existing wires, switches and placement sites used for routing an FPGA. With this graph, optimization and placement are driven by wire delay and actual availability of resources, rather than by measuring distance alone.

Graph-based physical synthesis merges optimization, placement and routing to ensure critical paths of a design use the fastest routing resources available. This push-button physical synthesis flow generates a fully placed and physically optimized netlist ready for input to the FPGA vendor's routing tool.

"By using the graph-based physical synthesis technology in Synplify Premier we were able to reduce the delay in our complex Xilinx Virtex-II Pro design from 14ns to 8ns without any floorplanning," said Bjorn Halfen, senior design engineer at Dolphin Interconnect Solutions, who used the Synplify Premier software in a recent project.

The automated graph-based physical synthesis flow within the Synplify Premier software supports Xilinx Virtex-4, Virtex-II Pro and Spartan-3 FPGA devices.

The Synplify Premier software also provides a method of finding functional errors in FPGA designs by providing simulator-like visibility into operating FPGA hardware.

Synplicity's integrated debugging software allows designers to annotate signals and conditions they want to monitor directly in their RTL code. Nodes that may be used as breakpoints and watch points are displayed for easy menu-driven instrumentation, and then seamlessly run through synthesis and P&R to implement the FPGA. Once the FPGA has been programmed, the RTL debugger is run, allowing users to view actual signal values from a running FPGA directly in their RTL code and debug it, in-system, and at the target operating speed. The tool offers advanced triggering that helps pinpoint design problems that could take a simulator days or weeks to uncover.

The Synplify Premier software is available now. Pricing for the software starts at $34,000.

- Ismini Scouras

eeProductCenter




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