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HDL tool suite cuts cycle times, respins

Posted: 11 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:mentor graphics? checking and creation environment? hdl designer series? tool suite? asic?

Mentor Graphics Corp. announced the release of a new concurrent design checking and creation environment, available in the latest version of the HDL Designer Series tool suite. Widely adopted as the most effective HDL design solution for ASICs and fpgas, said the company, the HDL Designer Series environment equally benefits individual engineers as well as large design teams, significantly reducing cycle times and respins.

"Concurrent design checking fundamentally changes the design paradigm. This is analogous to the way in which spelling and grammar checkers have changed the way we create written correspondence, sharply reducing the need for manual review," shared Glenn Perry, GM of Design Creation Business Unit, Mentor Graphics. "Our approach to concurrent design checking, combined with blazing fast speed of analysis and error isolation, enables companies to identify and rectify potential defects before they become more expensive to fix downstream."

With this new release, HDL Designer fully integrates what is touted to be the industry's first high-speed HDL design checking engine, optimized to operate real-time and concurrently during design creation. The release also supports advanced design and verification languages such as SystemVerilog and Property Specification Language (PSL), and provides expanded documentation capabilities via Adobe Systems' Scalable Vector Graphics (SVG) output.

Mentor Graphics added that unlike traditional post-process, batch-oriented linting tools, the configurable, high-performance HDL checking features in HDL Designer are easy to use and extraordinarily fast, thus enabling real-time analysis. The parameterized rule capability makes it far easier to configure the tool to do what any particular design team needs without initially spending a lot of time preparing rule sets. Moreover, checking for design reusability when the code is originally written helps deliver the productivity promise of reuse, by reducing the need to change and re-verify the code for every subsequent design in which it is used.

The HDL Designer Series is available immediately with pricing starting at $6,400 for a node-locked license and $9,600 for a floating license. It is compatible with all major OSes for maximum flexibility and ease-of use. The following platforms are currently supported: Linux Redhat/SuSE, Sun Solaris, HP-UX, and Windows 2000, XP and NT 4.0

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