Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Debugger improves FPGA power, speed and size tradeoffs

Posted: 12 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:mpulse accelerated technologies? codeveloper pro? c-to-fpga compiler?

Impulse Accelerated Technologies has released its CoDeveloper Pro optimization and debugging software to complement its CoDeveloper C-to-FPGA compiler.

The Pro tools add optimization and cycle-accurate debugging capabilities to improve quality-of-results for FPGA-based software and hardware acceleration.

"CoDeveloper Pro allows C programmers to have immediate, interactive feedback on their software-to-hardware programming choices and to quickly test different C coding styles and optimization selections," said David Pellerin, chief technology offer at Impulse, in a statement. "These tools, when combined with the CoDeveloper C-to-hardware tools, speed and simplify the process of optimizing and debugging C applications intended for hardware implementation."

The Pro tools can be used to explore the effects of loop unrolling, pipelining and stage delay strategies with the goal of increasing overall system speed. During this process, the developer may discover that a particular look or C software process can achieve higher overall throughout at a lower clock speed. As a result, power consumption is lowered with only a nominal increase in generated hardware resources through automated pipelining and instruction scheduling.

"This level of analysis through experimentation would be virtually impossible using traditional HDL coding methods," Pellerin said.

After hardware is generated in the form of automatically generated VHDL or Verilog output files, the application developer can further analyze the application by using the CoDeveloper Pro debugger.

The CoDeveloper Version 2 is available now with prices starting at $4,995 for a perpetual, single-user license. The CoDeveloper Pro Tools are an add-on option with prices starting at $2,495.

- Ismini Scouras


Article Comments - Debugger improves FPGA power, speed ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top