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Speeds grow for configurable CPUs

Posted: 17 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:tensilica? toshiba? risc core? soc? xtensa?

Tensilica Inc. has long made the argument that a small, efficient RISC core with instruction extensionsgenerated automatically along with its testbenchcan be a viable alternative to custom hardware development. The argument has rested on the idea that one can write out an algorithm in C, separate it into the non-critical 90 percent and the critical 10 percent, and then accelerate those critical inner loops with custom instructions. The overall gain in application throughput, often one or one and a half orders of magnitude, comes close to what could be achieved with a non-programmable data path, while keeping the application in software.

Inherent in this argument was the idea that the really heavy lifting would be done by specialized hardware generated to accelerate the inner loops. The rest of the code would run on a not-particularly-blazing vanilla RISC engine.

But as SoC designs tentatively move toward 90nm and as a few leading design teams explore 65nm, this underlying assumption may have to change, since the self-consciously simple and streamlined RISC cores that host the special hardware are themselves achieving unprecedented speeds.

This fact was clearly illustrated as Tensilica rolled out its 90nm Xtensa cores and tool flows, along with the silicon partners necessary to bring them into production. Setting aside any discussion of instruction-set extensions, the basic Xtensa core in its seven-stage-pipeline version simulates to a worst-case clock rate of 655MHz in TSMC's 90GT process.

This is not a result of hand-tuning a design using all the fastest transistors and disregarding yields, according to Tensilica president and CEO, Chris Rowen. It is the stock core using standard libraries and margining as recommended by the foundry. "We have been generally conservative with respect to process variations," Rowen said. "That leaves some upside for customers who really want to tune for performance."

Neither has the core grown huge in its speedthe seven-stage core occupies 0.224mm?. And with the elaborate power- and clock-gating technology that has been part of the Xtensa core since the 130nm generation, energy consumption can also be held in check, at least to the extent possible with 90nm G-type processes and at the specified frequencies.

"We spent a lot of time going through the RTL, better optimizing the paths," Rowen said, "and a large amount of time also went into working with our EDA partners and their tools to tune the scripting for the different balance you find in 90nm libraries." That work proved sufficient to avoid extending the pipeline beyond seven stages.

Toshiba's entry

Toshiba Corp. has divulged its own fast, small, configurable RISC core for use with its 65nm ASIC. The core, in a form that includes caches, debug hardware, DMA controller and DSP extensions (and does not provide an apples-to-apples comparison with the Tensilica numbers), measures about 1.6mm x 3mm on a 65nm die and clocks at around 1GHz, based on static timing analysis.

At the speeds of the new cores, considerable effort has to go into ensuring that the user-specified extensions can keep up with their host CPU. This mandates a careful analysis of path delays, memory latencies and the degree of pipelining and physical placement of the extension hardware.

The cores force yet another change in architectural thinking: When a task offers data or algorithmic parallelism, it may make sense simply to throw a handful of 500MHz to 700MHz CPUs at it without analyzing the inner loops for possible instruction-set extensions.

Even multithreading becomes more complicated. Assuming that the algorithm creates enough downtime to provide execution windows for additional threads, one still has to ask how much die area is involved in replicating just the register set compared with replicating the whole processor, Rowen observed.

- Ron Wilson

EE Times




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