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Self-learning switching DC/DC converters meet smart power

Posted: 17 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:power supply? inductor current? current-sensing technique?

By Gabriel A. Rincsn-Mora, Senior Member, IEEE
H. Pooya Forghani-zadeh, Student Member, IEEE
Georgia Tech Analog and Power IC Design Lab

High-performance, state-of-the-art applications demand smart power supplies to be adaptive, power efficient and reliably accurate, which is why monitoring inductor current flow in a lossless fashion is desirable and critical for protection, power-moding, and feedback control.[1,2] A handful of lossless current-sensing techniques are available today but their accuracies still do not compete with the traditional series sense-resistor schemes, and that is, for the most part, because the current is sensed by estimating the impedance of some series element and extrapolating the value of the current from the voltage across it, as Ohm's law dictates.[3]

Estimating the power MOSFET's turn-on resistance Ron, for instance, is inherently inaccurate because of its wide process, supply voltage, and temperature dependence, varying from approximately 50% to 200%. Additionally, the measured current only flows within a portion of the period, which requires a switched sample-and-hold circuit, another noise-generating device. Using an embedded current-sensing MOSFET, a power transistor's sister mirroring device sourcing a small fraction of the current (i.e., mirror ratio of typically over 1,000), is better with regard to accuracy but still inaccurate and also discontinuous, and only practical for on-chip power devices. Although accuracies of 14% are reported,[4] mismatch and process sigma variations across such a large spread of mirroring devices can reach 20 percent.[5]

The only continuous and therefore less noisy and more useful scheme for current-mode switching supplies is the matched-filter method.[6] In this scheme, the series impedance of the inductor and its equivalent series resistor (ESR) (that is, Ls + ESR) is matched against the series impedance of an RC network (for example, R + 1/Cs). Since both impedances are equal and they are subjected to the same voltage, their currents are also equal, which is why the displacement current through the RC filter is a direct measure of the inductor current. The accuracy of this technique, however, depends on how well matched the RC network is to the inductor-ESR combination, and that can lead up to 28 percent error, given 15 percent inductance, 11 percent ESR, and temperature (for example, 70C) variations, and more if extended to commercial and military temperature ranges. The RC filter is therefore external to the controller IC and typically custom-designed.

Knowing the inductance
How can IC designers know the impedance? They can't but the circuit can learn it during start-up and/or through power-on reset events; in other words, the system can measure the inductance-ESR impedance during down-times. Figure 1 illustrates how this approach can be applied to a buck (step-down) DC-DC converter using the above-described continuous filter scheme, where VSense is directly proportional and calibrated against inductor current IL. The shaded block is the Gm-C filter whose gain-bandwidth product is tuned with transconductor gm1 and DC gain calibrated with resistor R2 during a system down-time, aided by transistors Ma and Mb, both of which are off during normal operating conditions. The rest of the circuit is simply the power train of the switching supply, comprised of inductor L and its ESR RL, output capacitor Co, and high and low power MOS transistors ML and MH. Once the gain-bandwidth product and DC gain are properly adjusted (that is, filters are matched), the values are digitally stored and the DC-DC converter is allowed to power up and operate normally. Since the learning cycle only affects start-up, their associated power losses are non-existent during normal operating conditions, which is why this scheme is considered lossless.

Figure 1: Self-learning current-sensing Gm-C filter

The design and self-learning goal of the filter scheme is to match the series impedance of the inductor-RL combination with the R2C filter during the learning cycle. Following Ohm's law, inductor current IL is inversely proportional to its series impedance and directly proportional to the voltage across it (VL):

The R2C network, in this case, is a Gm-C filter with output voltage VSense equal to:

Consequently, adjusting R2 to ensure inductor current bandwidth RL/L equals filter bandwidth 1/R2C sets VSense to:

VSense = (gmlR2RL) IL how does this look?

and if gm1R2RL is tuned to a known constant RSense, VSense is a direct measure of inductor current IL,

To set these conditions, the circuit is subjected to a programming sequence during its down-time, but only after all start-up and power-on-reset functions are asserted and stabilized. First, a triangular current with a frequency significantly higher than inductor and Gm-C bandwidths RL/L and 1/R2C, respectively, is injected into the inductor-RL network to ensure resistances RL and R2 are negligibly smaller and larger than the inductor and capacitor's impedances, respectively (Figure 2). Consequently, a mostly square waveform appears across the inductor (that is, VL L dIp/dt ), which the gm1/C filter integrates back into a triangle (that is, dVSense/dt Igm1/C),

The ac portion of VSense is compared against VTune and the counter gradually tunes gm1 until the peak of VSense equals VTune, at which point the filter gain-bandwidth product (that is, gm1/C) is set, setting and storing gm1 to:

where IPeak is the peak value of the triangular input test current.

Figure 2: Tuning circuit

The end of the tuning cycle marks the onset of the calibration phase, at which point a DC test input current equal to IPeak is injected into the inductor-RL network, as shown in Figure 3. The impedance across inductor L and capacitor C at DC are significantly smaller than RL and larger than R2, respectively. The resulting sense voltage is therefore:

which is subsequently compared against VTune. Like before, the counter cycles and adjusts R2 until VSense is equal to VTune, setting the DC transimpedance gain (that is, RLgm1R2) of the network, or:

where the previously set gm1 (Equation 6) is substituted in. The new relation satisfies the original intent of equating inductor current bandwidth RL/L to filter bandwidth 1/R2C, and by setting VTune/IPeak to known constant RSense, gm1R2RL is similarly defined to RSense:

and Equation. 4 is satisfied.

Figure 3: Calibration circuit

In spite of self-learning, bias-induced and trimming accuracy errors still exist in the system. Current density and temperature settings, for instance, change from the self-learning sequence to the normal operating mode (the test current is for the most part smaller than the load current because of power and associated on-board real-estate concerns). These errors can be adjusted empirically, but not exactly. A first-order temperature dependence, for example, can be superimposed onto RSense. The input-referred offset and linearity of the transconductor across its wide input-common mode range (ICMR) will also impose errors. A linear, low offset transconductor with wide ICMR limits is therefore required. Nevertheless, a PCB prototype implementation of the technique presented exhibited overall full-load DC and AC gain errors of less than 2.3 percent and 5 percent , respectively, which is significantly better than previously reported lossless techniques.[7] A complete on-chip prototype is currently under development.[8]

For additional details, questions, and/or comments on this article, please contact us, the Georgia Tech Analog and Power IC Design Lab, at gtap@ece.gatech.edu. More information about our research can be found at http://www.rincon-mora.com/research.

References

[1] R. Erickson and D. Maksimovic, Fundamentals of power electronics. Norwell, MA: Kluwer, 2001.

[2] M. Gildersleeve, H. P. Forghani-zadeh, and G. Rincsn-Mora "A comprehensive power analysis and a highly efficient, mode-hopping DC-DC converter," in Proc. 2002 IEEE Asian Pasific-ASIC, pp. 153-156.

[3] H.P. Forghani-zadeh and G.A. Rincsn-Mora, "Current-sensing techniques for dc-dc converters," in Proc. 2002 Midwest Symposium on Circuits and Systems, pp. 577-580.

[4] C. Lee and P. Mok, "A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique," IEEE Journal of Solid States Circuits, vol. 39, January 2004, pp. 3-14.

[5] P. Drennan and C. McAndrew, "Understanding MOSFET mismatch for analog design," IEEE Journal of Solid States, pp. 450-459, March 2003.

[6] E. Dallago, M. Passoni and G. Sassone, "Lossless current sensing in low voltage high current dc/dc modular supplies," IEEE Trans. Industrial Electronics, vol. 47, pp. 1249-1252, December 2000.

[7] H.P. Forghani-zadeh and G.A. Rincsn-Mora, "A Lossless, Accurate, Self Calibrating Current-Sensing Technique for DC-DC Converters," IEEE's Industrial Electronics Conference (IECON), Raleigh, North Carolina, Nov. 6-10, 2005.

[8] H.P. Forghani-zadeh and G.A. Rincsn-Mora, "A Low Glitch, Continuous Low-Offset, Programmable Gain and Bandwidth, Gm-C Filter," IEEE's 48th Midwest Symposium on Circuits and Systems (MWSCAS), Cincinnati, Ohio, Aug. 7-10, 2005.





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