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Cadence backs IEEE P1647 e standardization

Posted: 20 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:cadence? lsi? standard verification language? ieee p1647? ieee?

Responding to user demand for a standard verification language, Cadence Design System, Inc. announced their support for the IEEE P1647 e standardization effort. Cadence also contributed resources for technical editing and program management to ensure the standard is of the highest quality and completed on time.

The e language is a powerful and mature system-level verification language used by the majority of industry leaders in consumer electronics, telecommunications, semiconductors and IP. By standardizing the language within IEEE and opening it to developments, customers will benefit as market-leading products are joined by growing marketplace of e-based tools.

"LSI Logic has proven expertise in e and advanced verification methodologies on complex IP blocks and entire systems. We have a significant interest in the standardization of e and participated in the drive toward e standardization by joining the LicenseE program in 2002," said Jeff Vanderlip, director of ASIC Marketing at LSI Logic. He added that LSI Logic salutes Cadence's support for e standardization effort and that they would like to see the standardization of the e language so as to have it open and available for everyone.

ARM Design Technology director, John Goodenough said, "ARM is fully supportive of the IEEE P1647 e standardization effort and standards in general. e had been an integral part of our verification methodology and it is good to see it move closer to standardization." He stated the process will encourage the proliferation of competitive tools and will be extremely positive for their partners since it ensures the stability of e and provides them with a choice of tools.

With its "Incisive" verification platform, Cadence provides the only multi-language verification technology. Their all-inclusive position on verification languages benefits customers by allowing each specialist an optimal blend of e, SystemC and SytemVerilog languages. As the industry continues to make standards, each language will emerge and find its optimal place in the verification landscape based on its strengths.

"With project and process level automation becoming more and more critical, Cadence has come to the realization that the best way to support customers is to offer support for standards that address the needs of each specialist in the verification process," explained Victor Berman, director of Language Standards at Cadence. He added that they support choice and do not subscribe to the approach that dictates to the users the language they must use for a given task.

If the ballot on the eLRM passes, the functional verification language is expected to be standardized by the IEEE by March 2006.

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