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RFICs invoke a paradigm shift

Posted: 20 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:cmos technology? rfic? sige-bicmos? si-bicmos? rfic?

By Cedric Paillard
Semiconductor Insights

Penetration of CMOS technology is increasing in RFICs, replacing relatively expensive processes such as SiGe-BiCMOS and Si-BiCMOS. One industry analyst predicts that CMOS will be employed in 40 percent of handsets shipped by 2009. The advantages of lower cost and greater integration with baseband functions are the main economic drivers, but converging markets are also feeding the RFIC industry growth. With a predicted market for RF components of $7 billion in 2009, technology innovations are also driving towards new architectures and new solutions, enabling the industry to come up with reusable blocks, higher performance, lower power consumption, and potentially new business models.

The heterodyne or IF receiver is the best known and most frequently used receiver architecture. However, this architecture has recently reached its limitations due to its poor degree of integration as every stage requires going off-chip and the use of costly and high-power discrete band-pass filters.

The homodyne or Zero-IF and its derivative receive architecture (quasi-IF, wideband-IF, high-IF) are potential alternatives due to their higher integration and small die area. The transition from heterodyne to homodyne architecture is significant enough to be noted but the key paradigm shift is the increase use of the digital signal processing (DSP) to compensate for the quirks of those topologies. DSP is now used to increase VCO tunability, to provide better filtering, and decrease power consumptions by moving functionalities to the digital domain.

The synthesizer paradigm shift
The synthesizer (with the local oscillator, or LO) helps select the correct frequency in the up- and down-converters. Low power consumption/low cost requires a completely integrated (no external components) synthesizer. Recent wireless standards are characterized by small signal, whereas adjacent channels can have large power levels, increasing the importance of the phase-noise specifications for the LO signal.

With LC oscillators, the phase noise is inversely related to the power consumption, making this the topology the best choice for a low-power, low phase noise VCO. The only limitation is its dependence to the integrated passive inductor. Three solutions exist: spiral inductors on a silicon substrate combined with digital techniques that increase the Q-factor; bond wire inductors for low phase requirements and high-Q; and a spiral coil combined with highly doped substrate.

For the synthesizer design itself, an all-digital PLL coupled with a digitally controlled oscillator has been introduced across multiple wireless platforms. Once again, the combination of a tight collaboration between RF designers, process engineers, and digital/software designers is a key to easy tuning and trimming as well as the post-processing that's required and for today's telecom specifications.

Transmitter architecture paradigm shift
The transmitter's purpose is to multiply the LO and baseband signals to form a high-frequency output signal. All further signal processing must be performed at high frequencies, which is difficult and power consuming in CMOS. Most of the latest transmitter architectures rely on direct conversion, but more so on pre-conditioning the transmit signal in the digital baseband to reduce analog footprint on the die and improve performance (Figure 1).

Figure 1: The traditional radio architecture is mostly an exercise in analog design.

This design methodology shift is a particularly visible wireless solution requiring high data rate with multi-carrier waveform (because of the high peak-to-average power ratio), but it also becomes more visible in less complex devices to improve performance and decrease power consumption (Figure 2). With multi-carrier waveforms signal, help from digital pre-conditioning is needed to increase the power amplifier efficiency.

Figure 2: The digital radio offers a more straightforward design.

Technology paradigm shift
Technology is scaling down to 90 nm CMOS today and 65 nm within the next two years. Requirements to achieve higher integration levels are pushing process engineers to work closely with RF engineers to come up with new architecture relying on the speed increase achieved with deep sub-micron technology while avoiding the pitfalls of increased parasitic capacitance.

At the recent RFIC2005 conference, an expert from TI's wireless analog technology center said, "When designing highly integrated RF circuits in deep submicron CMOS processes, we're faced with the paradigm shift that the time domain resolution of a digital signal edge transition is superior to the voltage resolution of analog signals."

In addition, new application-specific processes are being developed. For example, new processes support a range of different threshold voltage transistors that can be combined to optimize circuitry for power consumption or high performance. Transistors are also optimized for analog and mixed signal blocks if necessary, and high-density MIM capacitors have been developed. In the short term, the technology isn't a limiting factor. However, packaging has revealed itself to be more important than previously anticipated.

The role of IP
The role of intellectual property (IP) became an important aspect of the RFIC design. As these designs become more digital, flexible, and configurable, the exchange and cross licensing of IP is key to speeding up the process of full radio integration. With respect to RFICs, we're seeing a significant shift where reusable IP across wireless platforms is possible (and vital) to speed up the radio design and integration process. For the first time, process and package technologies seem to be in phase with design techniques to enable the reuse of RF (now digital) building blocks. RFIC makers that aren't embracing this paradigm shift may pay a heavy penalty in the future and might never recover, leaving the door open to new comers.

Following ten years of pioneering work in digital RF, the RF industry is entering a new phase with more collaboration between circuit and process designers. The result of this collaboration is the launch of digital radios in commercial products with improved performances and at cost/price levels that are acceptable by the market. Soon, new tools focusing on the interface between blocks, crosstalk techniques, etc., for digital radio blocks/IP integration will appear, shifting the complexity of RF design to RF integration. Because digital blocks are easier to manage and integrate, the RF industry will go through an alignment phase with new business models for this digital-radio market.

About the author
Cedric Paillard
is a director at Semiconductor Insights. He holds BS and MS degrees in VLSI System Engineering from the University of Manchester Institute of Science and Technology. He also has a Bachelor of Engineering from the Ecole Superieure de Technolgie Electrique. Paillard can be reached at

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