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IMEC proposes sandwich substrate to extend CMOS era

Posted: 24 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:cmos? imec? sandwich substrate?

Researchers at IMEC have proposed that multi-layer substrates comprised of gallium arsenide grown over germanium grown above silicon, together with novel gate dielectrics and metal gates, could be the best way to extend the use of CMOS into the sub 45nm device era.

The approach, outlined to representatives of the press by IMEC Fellow Marc Heyns, would use gallium arsenide, a III-V compound semiconductor grown over germanium, a type IV semiconductor, grown over a silcon substrate used primarily as a low-cost carrier, but also available for the implementation of lower perfromance mature technology transistors.

Although the International Technology Roadmap for Semiconductors (ITRS) is shown scaling down to a 22nm node there are no known solutions for gate dielectrics below the 65-nanometer node that meet its parameters in terms of scaling the effective oxide thickness, Heyns showed. And problems with the development of metal-gates for use with hafnium-based high-k dielectrics are leading researchers at IMEC (Leuven, Belgium) to consider that alternative substrates and semiconductor materials are required for the devices that would be introduced in the decade beyond 2010.

Heyns said that so far the semiconductor industry has substantially been based on the attributes silicon dioxide, the simply-structured insulator which is easily grown on top of silicon. Heyns added that as the industry is now being forced to consider alternative and much less well understood insulators, which do not integrate easily with silicon, it calls into question the use of silicon in the long term.

As to the near term the selection of well-characterized metal gates to sit over a hafnium-based gate dielectric is proving difficult, Heyns said.

"The correct metal-gate? We're still looking for it." One issue is that the work function of the metal-gate materials investigated tends to shift with annealing temperature towards a mid-point, Heyns said.

"EOT [effective oxide thickness] is not possible at 0.8 [nanometers]," Heyns said despite the fact that the ITRS calls for an EOT for logic processes of 0.7 nanometers at the 45nm manufacturing process node. "Whether the 45nm node meets the roadmap is up to manufacturers," Heyns said in answer to the suggestion that Intel has opted to defer the use of high-k dielectrics and metal gates at the 45nm node.

Partly because of these difficulties and partly in fulfillment of the research institute's charter to investigate the ten-year horizon IMEC's researchers have started work on yet higher-k dielectrics. These are scandium oxides of a variety of lanthanoid elements; namely gadolinium, dysprosium and lanthanum scandate. These materials have the advantage of remaining amorphous to high temperatures, Heyns said.

Heyns continued by saying that very good results had been obtained for novel high-k material directly deposited on germanium as part of a trial of complementary FET structures. The gallium arsenide is used for the n-type FET and the germanium for p-type FETs.

"Very encouraging initial results were obtained for the selective growth of gallium-arsenide over germanium," Heyns said. The germanium p-type devices were made with gate lengths of 150nm while the gallium arsenide n-type devices were above a micron, he added.

The selective local deposition of the semiconductor layers was done using a Thomas Swan metal-organic chemical vapor deposition reactor with molecular beam epitaxy used to deposit unnamed high-k materials.

Heyns declined to confirm that the high-k dielectrics were scandate materials and said that IMEC would not be presenting learned papers on the topic in the near future. IMEC researchers have collaborated with the Demokritos research institure in Greece on this subject.

Heyns conclusion was that high-k insulator and metal-gate solutions are available for next-generation manufacturing processes but that higher-k materials and alternative substrates offer the potential for further enhancement of transistor performance.

- Peter Clarke

EE Times

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