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Freescale exec says centralizing design activity paying dividends

Posted: 25 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:freescale? ic design? chip design?

Changes in Freescale Semiconductor Inc.'s approach to chip design, including standardizing on methodologies and appointing a renowned design manager, are contributing to improvements in the company's bottom line, according to Sumit Sadana, senior vice president of strategy and business development.

Sadana told EE Times Friday (Oct. 20) that, since joining Freescale in December 2004, he has implemented several changes to centralize design activity within the company in support of Freescale's overall goal of reducing cost structure and improving efficiency.

In addition, Sadana credited the addition of Chekib Akrout, the former IBM vice president who headed the design effort on the Cell processor, with adding experience, leadership and star power to Freescale's design efforts. Akrout quietly joined Freescale several months ago as vice president of design systems.

Freescale, which had been Motorola Semiconductor prior to being spun out by the parent company last year, had traditionally maintained a very de-centralized design function, Sadana said, with design teams that were segregated mainly by product division. Each, he said, operated completely autonomously from the others, selecting their own EDA tools (and suppliers), methodologies and practices. This situation resulted in a mismatch of tools and technologies, and left the company with little leverage for negotiating volume license agreements with EDA vendors.

Sadana has created a centralized design technology organization, responsible for design teams across Freescale's divisions. This organization is in the process of creating a common methodology, including standardizing on a set of EDA tools.

"It's still a work in progress," Sadana said. "But we've been at it for many months."

Though he would not reveal the vendors involved, Sadana said Freescale is close to signing some very significant deals with a much smaller set of EDA providers than the company had been using previously and that, over time, Freescale's EDA tool vendor base would decrease. These pending deals, he said, are more "partnerships" that include the sharing of Freescale and legacy Motorola internal tools and intellectual property.

Sadana said the design centralization effort, though still evolving, has already paid dividends. As proof, he pointed to the company's recent announcement that its first dozen 90nm products have all been "right-the-first-time," producing fully functional samples in customers applications after only one pass.

Like many companies, Sadana said, Freescale is also putting greater focus on design-for-manufacture (DFM) and design-for-test (DFT) in order to increase yields, reduce test times and "not build un-testable chips." In support of these efforts, Freescale is including more built-in self-test (BIST) structures in designs and is moving to standardize on one tester platform company-wide, Sadana said.

On Thursday, Freescale reported a third quarter net income of $164 million on sales of $1.45 billion. Sadana touted the company's third quarter improvements in gross margin (to 43.3 percent) and operating income (to 10.6 percent) as indications that Freescale is succeeding at its goal to strengthen its operating model.

Also Thursday, Freescale announced the acquisition of modem processing multimode IC provider CommASIC, which Freescale has converted into its San Diego Design Center. Sadana said Freescale would "almost certainly" be announcing other acquisitions in the near future and that the company would "not be shy" about making acquisitions to acquire technology and talent.

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