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Survey finds verification tool use largely unchanged from 2004

Posted: 27 Oct 2005 ?? ?Print Version ?Bookmark and Share

Keywords:verification? formal verification? verification tool?

The 2005 "verification census" survey conducted by John Cooley of EDA tool user Web site found that little has changed in verification tool and intellectual property (IP) usage from 2004.

The survey results, published Tuesday (Oct. 25), were "jaw-droppingly" similar to the 2004 survey results, Cooley said. "It shocked me how much stuff did not change," Cooley said.

The survey was sent out twice in March to the 22,000 people found on the list of the e-mail Synopsys user's group (ESNUG), which Cooley also moderates. A total of 338 people responded to all 11 questions posed by the census. In 2004, only 147 people responded to all 11 questions.

In one notable exception to the consistency with 2004, 47 percent of respondents say they are now using Synopsys Inc.'s VCS or VCS-MX simulators, up 13 percent from 2004. Cadence Design Systems Inc. maintains a slight lead in the category, with 51 percent of respondents indicating that they use one of the company's Verilog or VHDL simulation products, the same percentage as found in 2004. The number of respondents who indicated that they were using a Mentor Graphics Corp.'s ModelSim declined 6 percent to 35 percent. (Because users may be using more than one product, category totals do not add up to 100 percent).

The number of respondents who indicated that they would be using SystemC in the next six months increased by 10 percent from 2004 to 42 percent. The survey noted that 43 percent of respondents that are currently using SystemC indicated that they are using Cadence SystemC tools. By contrast, only 17 percent said they were using Mentor tools and only 10 percent said they were using Synopsys tools.

Eighty-one percent of 2005 respondents indicated that they would not be using System Verilog in the next six months, up 2 percent from 2004.

Seventy-eight percent of respondents said they expect functional verification languages Specman "e" and Vera to be dead in five years. In 2004, 81 percent of respondents said they expected the languages to be dead in five years. In a change from 2004, Cooley said, the majority of respondents indicated that they believe System Verilog will succeed Specman "e" and Vera.

The survey found that Cadence's Palladium maintains a sizeable advantage (14 percent overall, and 59 percent among the companies that use them) over competitors in the emulator/accelerator space. But overall, 78 percent of respondents said they either does not use hardware emulators/accelerators or use internally developed field-programmable gate arrays (FPGAs) instead.

Cooley said that one of the things that surprised him about the survey results was in the area of assertions, where the number of respondents who said that they use IBM Sugar/PSL dropped from 34 percent to 21 percent, more in line with the percentage of respondents using System Verilog SCA (18 percent), Verplex OVL (14 percent) and Synopsys Vera OVA (12 percent).

The number of respondents that rejected hardware/software co-simulation grew up 6 percent in 2005 to 87 percent.

The number of respondents who indicated that they do not use verification IP stayed consistent, dipping by 1 percent to 47 percent, remaining nearly half of all respondents.

Among the survey results, Cooley also included several respondent comments to Calypto Design Systems Inc.'s system-level equivalence checker (SLEC) family of products, which was introduced in April. Cooley said Calypto was singled out purely because the company is a new player on the scene.

The full results of the census on design verification tool use can be found here.

- Dylan McGrath

EE Times

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