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Xilinx unveils free RPR MAC reference design for Virtex-4 FPGAs

Posted: 02 Nov 2005 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? rpr mac reference design? virtex-4? fpga?

Xilinx Inc. announced a free RPR MAC reference design for use with its Virtex-4 family of domain-optimized FPGAs. This new solution implements a complete RPR MAC supporting all key features of the IEEE 802.17 specification, including MAC data path for east and west, Fairness, Topology, Protection and OAM. According to Xilinx, flexibility is provided through support for 1G, 2.5G and 10G rates, various PHY side interfaces (GMII, SPI-3, SPI-4.2, XAUI and XGMII), memory interfaces, and a host of client interfaces. High availability is achieved via built-in functionality for equipment protection/redundancy.

The Virtex-4 family is revolutionizing the fundamentals of FPGA economics, said the company. With three application-domain-optimized platforms and a selection of seventeen devices, this FPGA family promises to deliver breakthrough performance at the lowest cost and offer a compelling alternative to ASICs and ASSPs.

The RPR MAC reference design is available free of charge at Xilinx's website. The design package includes the design netlist, software drivers and complete documentation including a compliance matrix.




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