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Integrate flash device programming, reduce cost

Posted: 01 Nov 2005 ?? ?Print Version ?Bookmark and Share

Keywords:eprom? eeprom? flash? storage? pld?

In the late 1980s, memory devices changed in a flash. Intel and Toshiba spearheaded the development of flash process technology to create a new class of products.

Low-cost standard flash memory devices are commonly used in a variety of applications to store configuration, program or memory data. Before flash memory devices can be used in a system, they must be programmed. Using traditional methods, programming may require large amounts of time in the manufacturing process. As storage densities for flash memory devices continue to increase, programming times also increase. Traditional methods provide little flexibility for last-minute design changes or programming updates while the product is in the fieldcapabilities that are increasingly required to add features or address bugs.

Traditional options

There are three options for programming today's flash memory devices. The first is to pre-program the device before inserting it onto a PCB. This approach increases the cost of manufacturing, since it requires extra fixtures to program the device. Another limitation is that, once pre-programmed and mounted, the device cannot be used for other purposes as the design evolves. This option is also inflexible as it does not allow for last-minute changes, enhancements or bug fixes that may be necessary after the part is inserted onto the PCB.

The second is to program the flash memory device after it is installed on the PCB, also known as in-system programming (ISP). One way to accomplish this is to first install a small program into an existing microprocessor on the PCB and then have the microprocessor program the device. The microprocessor accesses the small program either in-system or through the use of in-circuit emulation hardware, adding extra equipment and another step to the manufacturing process. In this method, data transfer to the flash memory device is inefficient, since the microprocessor must first access the data from a different source, store it in any available RAM and finally program the device.

The third is to use ISP with a JTAG boundary scan chain to control the pins connected to the flash memory device. This option is often used because many flash memory devices do not support the JTAG interface due to cost and space limitations. In this approach, the flash memory device is connected to a JTAG-compliant device on the PCB, which acts as a programming host. A device such as an ASIC or PLD may be used as the programming host. This inefficient method requires shifting hundreds of bits of data through the entire JTAG boundary scan chain to write just a few bits of data to the flash memory device. Another limitation of this approach, when using a PLD host, is that it requires the host PLD to enter a programming mode. This causes the core of the PLD and other devices connected to it to temporarily cease functioning.

Shorten programming times

A parallel flash loader (PFL) solution provides an easy, cost-effective way to program flash memory devices through the JTAG interface. The JTAG test access port is found on most PCBs, since it only requires a small amount of space (four pins) to access all JTAG-compliant devices on the PCB. The solution uses a CPLD to bridge the JTAG interface and the flash memory device's parallel address/data interface. Instead of shifting data through all pins on the CPLD, this solution quickly retrieves data from the JTAG scan chain and generates data that is formatted for the receiving target flash memory device. Unlike the JTAG boundary scan chain method, the PFL brings the data through the logic array of the CPLD.

The solution reduces flash memory device programming time. In addition to shorter programming times, the PFL solution can be used to configure proprietary FPGAs on the same PCB, using FPGA configuration data stored in a flash device. The PFL logic determines when to start the configuration process, reads data from the flash memory device and configures the FPGA accordingly. The PFL also supports a proprietary page mode for FPGA configuration. Each page stores the configuration data for a single chain of FPGAs and up to eight different pages can be stored in a single flash memory device. Using this method, hardware developers avoid using dedicated FPGA configuration devices, reducing component costs, shrinking board size and simplifying board design.

This method can also be used with ASSPs and ASICs. In this case, the PFL can send configuration or initialization data to the flash device for ASSPs and ASICs, as in the FPGA scenario. The remaining logic in the CPLD can then be used to implement functions to execute configuration signals to these devices.

The PFL can be easily integrated into a CPLD using a simple GUI in the development software. The GUI enables the user to set the clock frequency, flash memory type, byte address of the option bits and desired supplemental files. The software automatically generates the needed logic for implementation in the device.

The PFL, along with proprietary CPLDs, offers several key benefits over existing flash programming options. This implementation takes advantage of real-time ISP, allowing for last-minute design changes, enhancements or bug fixes without sacrificing time-to-market. A new or updated programming file can be loaded at any time during the manufacturing process through the JTAG interface. The PFL solution offers the flexibility to easily make updates in the field without powering down the entire system. Another advantage of using programmable logic is design reuse. As data requirements and flash devices continue to progress, the PFL solution can still be used with little or no redesign effort required. Therefore, the PFL can easily be ported into new designs or the same design for different platforms.

The PFL method does not require special programming fixtures, since the proprietary CPLD uses the JTAG scan chain connections that are already present on the PCB. This results in a reduction in both manufacturing costs and time. Since the PFL only uses a small portion of logic in the CPLD, the remaining logic can be used for other applications such as I/O expansion, system configuration or power-up sequencing. Finally, the PFL function can fit into the smallest CPLD, resulting in a low component cost.

Flash memory devices offer great value to engineers who seek high-density, low-cost memory devices that are easy to program and erase. Using ISP with a JTAG boundary scan chain is often the method of choice for programming today's flash memory devices.

However, this approach has limitations, which include requiring considerable data shifting through the entire JTAG boundary scan chain to write just a few bits of data to the flash memory device. Using a PFL solution provides engineers with an easy, cost-effective way to program flash memory devices through the JTAG interface. A PFL solution offers benefits such as shorter flash memory device programming times, streamlining of the FPGA configuration process, ease-of-use and low adoption cost.

- Theresa Vu

Sr. Product Marketing Engineer

Altera Corp.

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