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New clock multiplier from TI cuts period jitter by up to 70 percent

Posted: 08 Nov 2005 ?? ?Print Version ?Bookmark and Share

Keywords:texas instruments? ti? clock multiplier? cdce706? rf?

TI's CDCE706

Texas Instruments Inc. (TI) unveiled a clock multiplier that integrates three on-chip phase locked loop (PLL) components to deliver "industry-leading flexibility and performance," including cutting period jitter by up to 70 percent compared to existing solutions and minimizing electromagnetic interference (EMI).

Each of the device's six outputs can be programmed in-circuit or during operation for any clock frequency up to 300MHz. According to TI, this flexibility eases the design process, saves system cost and maximizes designers' ability to meet emerging standards in high-performance communications applications such as wireless base stations and telecommunications or data communications equipment.

Developed in the company's radio frequency (RF) silicon-germanium process, the three PLLs of the CDCE706 can accept a crystal, LVCMOS or differential input and generate six clocks from a single clock source. Using on-chip EEPROM technology, designers can easily program and save the device's register settings in non-volatile memory so that no re-programming is required at power-up. Designers can also use the 2-wire SMBus interface to dynamically reprogram the outputs as needed while the device is in the system.

The CDCE706 enables fast time-to-market by easing the design process while providing low period jitter of less than 60ps. The user only needs to define the input and output frequencies or the divider setting, which automatically sets the PLL parameters. This in turn guarantees high loop stability and frees the user from manually setting the charge-pump current, filter components, phase margin or loop bandwidth.

In addition, the new device features very flexible output settings such as enable, disable, low-state, signal inversion, slew-rate control of 0.6ns to 3.3ns, and variable output supply voltage of 2.3V to 3.6V. Along with programmable spread spectrum clocking (SSC), these features provide designers a powerful tool to optimize their designs for the lowest EMI possible. Also, the device's high-resolution PLL dividers enable zero parts per million (PPM) output clock error for high frequency stability.

The CDCE706 is sampling today and will be in full production in 1Q 2006. Suggested resale pricing is $3.60 each in 1,000-unit quantities. A development kit and programming kit will be available to help simplify PLL design and programming. The CDCE706 will also be available in factory-programmed versions for high-volume applications. The device is 3.3V supplied, operates in the industrial temperature range of -40C to 85C, and is housed in a 20-pin TSSOP package.




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