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Underutilized SEPIC outperforms flyback topology

Posted: 16 Nov 2005 ?? ?Print Version ?Bookmark and Share

Keywords:sepic? power? supply? flyback? magnetic?

Designers are often given a set of non-isolated supply specifications where the output voltage falls between the minimum and maximum input voltages. They then have to decide between a flyback or SEPIC topology. The usual choice is flyback, mostly due to the lack of familiarity with SEPIC. However, this decision may not be the best design solution.

Table 1 presents a set of electrical specifications to power an automotive stereo system. The input voltage range is quite large at 10V to 40V. 10V is provided during heavy current draw and cold conditions, while a 40V surge can occur when the car's battery is disconnected. The output voltage of 15V is in the "middle" of the input voltage range, requiring a topology that can buck and boost the input voltage. The output power is approximately 26W, which could generate thermal issues if the power supply is not reasonably efficient.

Input Voltage10V!40V
Output Voltage15V
Output Current0.2A!1.75A
Dynamic Regulation\1 percent
Ripple1.5 percent
Efficiency85 percent minimum

Table 1

These specifications were used as the starting points to design and prototype the two candidate topologies. Figure 1 features the finished hardware. The two designs look similar, but the SEPIC's coupled inductor is larger than the flyback's. This larger size!and larger energy storage!is needed to keep the SEPIC converter operating in continuous-current mode (CCM) at light loads.

In a simplified schematic of the power stages for both topologies, the power switch Q3 is turned on to store an incremental amount of energy in the transformer. It is then turned off and the transformer's secondary voltage reverses. Current is forced through D6 into the output. An equal amount of energy from the transformer charges the output capacitor and is delivered to the load. Regulation is achieved by controlling the duty factor and the incremental energy into the system. Both the power switch and diode work in unclamped inductive switching!i.e. the voltage placed on them is controlled mostly by the transformer leakage inductance and stray capacitance.

When Q6 is on, the C26 positive terminal is held at ground, while the T2 one-to-one turns ratio places a voltage equal to negative Vin on the C26 negative terminal. This means that the capacitor has the input voltage applied across it with the polarity shown. In this circuit, when the switch is turned on, an incremental amount of energy is stored in the primary inductance. Current flows in the secondary inductor and coupling capacitor (C26) to equalize its charge. When the switch is turned off, the voltage on the Q6 drain rises. A current flow from primary (through C26) and secondary (through D9) is provided to the output.

Finished hardware

Figure 1

This circuit has the advantage that the FET and diode voltages are clamped by the capacitors, so there is little circuit ringing. It might seem that the SEPIC "pays a penalty," since the C26 coupling capacitor has significant ripple current. However, this ripple is offset by the much smaller ripple current from the C19 input capacitor's continuous input current. This topology has another advantage with power being simultaneously drawn from the input and delivered to the output, much like an autotransformer. Since the power switches do not have to handle the entire power transfer, the circuit is more efficient.

SEPIC requires a slightly larger output capacitance due to its larger duty cycle and longer diode off time compared to the flyback. Table 1 also shows FET and diode voltage stresses for both circuits. The flyback FET seems to have a lower "flat-top" stress. However, it must switch an unclamped inductance and will have significantly higher voltage stress than the SEPIC FET when this is factored in. The flyback diode peak inverse voltage (PIV) starts with a larger voltage stress than that of the SEPIC, but also has an unclamped inductive-switching spike, making it significantly worse.

In this example, the voltage stress makes a Schottky diode unacceptable for the flyback and forces the use of an ultrafast diode with higher conduction losses and correspondingly lower efficiencies. Voltage spikes on the power switch and output diode caused by the flyback transformer leakage inductance usually require a voltage clamp and snubber circuit to limit the peak voltage, further reducing efficiency.

The demo circuit schematic for the prototype hardware in Figure 1 occupies a component area of just over 3inches2. The SEPIC's inductor height is twice that of the flyback's tallest component. The inductor's form factor could have been designed to lie flat to reduce height, but at the expense of increasing the PWB's area. Except for the magnetics, both designs use similar power-stage components. Different controllers were chosen for each design. The flyback uses a UCC2813, which limits the duty-cycle to 50 percent maximum, while the SEPIC uses a UCC3807, which allows an adjustable duty-cycle limit greater than 50 percent. In this application, it is set to a 75 percent maximum. The flyback uses three input capacitors rated to handle the large AC-RMS requirement of the pulsating current generated by the FET switch.

Generally, large-value, low-cost aluminum electrolytic capacitors work well compared to ceramics, which don't have the capacitance necessary to provide low-input ripple voltage. In the SEPIC, only one input capacitor is required and must handle the AC-RMS rating of the triangular inductor current. This is a relatively low RMS current and capacitance value!a fairly easy requirement to meet. Two AC coupling capacitors are required on the SEPIC, which has the same stress equation as the flyback input capacitor, but is operating at a larger duty-cycle. This larger duty-cycle reduces the RMS current to two-thirds that of the flyback's input capacitors.

While the flyback converter's relative simplicity and familiarity have their advantages, the SEPIC converter can provide higher efficiency and lower component stress. The SEPIC is more efficient due to lower FET and diode stresses. The flyback has lower component area, since the SEPIC has larger magnetics. Component count is similar for the two designs, with an equal number of power components and similar number of support components. However, the flyback has the disadvantage of requiring snubbers. Continuous input current not only reduces ripple current rating of the SEPIC's input capacitor, but also helps improve a system's electromagnetic emissions. If there are other loads on the 12V input, the flyback's discontinuous input current is more likely to generate an unacceptable ripple on the input, requiring additional filtering.

Compared to the flyback, the SEPIC control loop characteristics are much less documented and not generally understood. A SEPIC operating in CCM and implementing current-mode control, as described, can present control-loop challenges. This involves compensating for a right half-plane zero and wide variations in closed-loop gain over input voltage and output loading. This can result in lower control-loop gain, which can degrade transient load performance. However, when implemented correctly, the SEPIC converter provides a high-efficiency solution.

John Betten
Robert Kollman
Texas Instruments Inc.

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