Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Reducing power consumption

Posted: 16 Nov 2005 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? power? consumption? management? xilinx?

As each generation of FPGAs gets increasingly faster, denser and larger, designers need to ensure that power doesnt increase as well. A number of design decisions can impact the power consumption of your system, ranging from the obvious choice of device selection to the more minute details of choosing state-machine values based on frequency of use.

Power comprises two factors: dynamic and static power. Dynamic power is that required to charge and discharge the capacitive loads within the device. It is highly dependent on frequency, voltage and loading. Each of these variables is under your control in one form or another.

Dynamic power = capacitance * voltage2 * frequency

Static power is the sum of power caused by leakage (source-to-drain and gate leakage, often lumped as quiescent current) for all of the transistors in the device, as well as any other constant power requirements. Leakage current is highly dependent on junction temperature and transistor size.

Constant power requirements would include current leakage due to termination, such as in a pull-up resistor. Not much can be done to affect leakage, but constant power may be controlled.

The decisions you make about power have the greatest impact in the early stages of your design. Deciding on a part can have huge implications on power, while inserting a BUFGMUX in a clock will have much less impact. It is never too early to start thinking about power for your next design.

The right part for the job

Not all parts have the same standby power. As a general rule, the smaller the device process technology, the faster the transistorsbut also the higher the power leakage. However, not all process technologies are created equal. For example, there are differences in standby power for 90nm technology between domain-optimized platform FPGAs and other 90nm FPGAs. The 90nm domain-optimized platform FPGAs incorporate a new process approach called triple-oxide technology to solve the static power problem by selectively increasing gate-oxide thickness to reduce leakage current without compromising performance. Although this third gate-oxide layer is still very thin, these transistors exhibit substantially lower leakage than standard thin-oxide transistors. According to studies, 90nm domain-optimized platform FPGAs consume 50 percent less static power than the previous generation of 130nm platform FPGAs.

However, as standby power rises and process technology shrinks, dynamic power decreases because smaller processes come with lower voltage and capacitance.

Some FPGA and CPLD devices have dedicated logic in addition to general-purpose slice logic cells. These take the form of block RAM, 18 x 18 multipliers, DSP48 blocks and SRL16s, among others. You should always use dedicated logic rather than its slice-based equivalent. Not only does dedicated logic have higher performance; it also requires less density and thus consumes less power for the same given operation.

Data enable

Chip select or clock-enable logic is often used to enable registers when the data on the bus is relevant to them. Take this a step further and data enable the logic as early as possible to prevent unnecessary transitions between the data bus and combinatorial logic to the clock-enabled registers.

Another option is to perform this data enable on the board instead of on the chip. For example, you can use a CPLD to offload simple tasks from the processor, allowing it to stay in standby mode longer. Applying this same idea to FPGAs is also feasible. Although FPGAs do not necessarily have a standby mode, using a CPLD to intercept bus data and selectively feed data to the FPGA can save unnecessary input transitions. Some CPLDs contain a feature called data gate, which disables logic transitions on the pin from reaching the internal logic of the CPLD. The data gate enable may be controlled either by logic on-chip or by a pin.

Clock management

Of all the signals in a design that can draw power, clocks are the largest offenders. Although a clock may run at 100MHz, the signals derived from this clock often run at a small fraction of the main clock frequency (commonly 12-15 percent). Also, the fan-out for clocks is naturally high so these factors show that clocks should be studied for purposes of power reduction.

If a section of a design can be in an inactive state, consider using a BUFGMUX to disable the clock tree from toggling instead of using clock enables. Clock enables will prevent registers from toggling unnecessarily. However, the clock tree will still toggle and consume power. But clock enables are better than nothing.

Isolate clocks to use the fewest quadrants possible. Unused clock-tree quadrants will not toggle, thus lowering the load on the clock net. Careful floorplanning may achieve this goal without affecting the actual design.

Power estimation tools

Xilinx provides power-estimation tools in two forms: a pre-implementation tool called Web Power Tools and a post-implementation tool called XPower.

XPower analyzes the actual device usage and, in conjunction with actual post-fit simulation data, delivers accurate power data. With XPower, you can analyze design changes for impact on overall power without touching a piece of silicon.

Web-based power estimation is the quickest and easiest way to get an idea of device power consumption early in the design flow. A new version of these tools is released every quarter, so information is current, and no installation or downloading is required. You can specify design parameters and save and load design settings, eliminating the need to re-enter design parameters with iterative use. Just an estimate of design behavior and a target device will get you started.

XPower is integrated directly into ISE software and gives hierarchical and detailed net power displays, detailed summary reports and a power wizard that makes it easy to run for new users. XPower can accept simulated design activity data and runs in both GUI and batch mode.

XPower considers each net and logic element in the design. The ISE design files provide exact resource use; XPower cross-references routing information with characterized capacitance data. Physical resources are then characterized for capacitance. Design characterization is continuous and ongoing for newer devices to provide the most accurate results. XPower uses net toggle rates and output loading. XPower then computes power and junction temperature, and can also display individual net power data.

Increasing demands for cheaper and simpler thermal managementas well as power supplies coupled with the increasing power requirements of cutting-edge FPGAshave elevated the concept of designing for low power to greater heights. Domain-optimized platform FPGAs offer the high performance of 90nm process technology without the assumed increase in static power. When used with power-estimation tools and considerations for low-power design, meeting your power goals is easier than ever.

- Arthur Yang

Sr. Product Applications Engineer

Xilinx Inc.

Article Comments - Reducing power consumption
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top