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Synopsys, UMC partner on low power 90nm reference flow

Posted: 23 Nov 2005 ?? ?Print Version ?Bookmark and Share

Keywords:taiwan? eda? umc? synposys? 90nm reference design flow?

EDA giant Synopsys Inc. and Taiwanese foundry United Microelectronics Corp. (UMC) Monday (Nov. 21) announced the availability of a 90nm reference design flow that is said to be optimized for low-power system-on-chip (SoC) designs.

The validated RTL-to-GDSII design flow is based on Synopsys' Galaxy design platform, ARM Artisan Sage-X standard cell library and UMC's 90nm process, the companies said. The design flow addresses leakage power challenges at 90nm and provides advanced design-for-manufacturing (DFM) capabilities for faster yield ramp and lower development costs, according to Synopsys (Mountain View, Calif.) and UMC (Hsinchu, Taiwan).

"This latest development with Synopsys is specifically designed to give customers the benefit of both companies' expertise to help them achieve first pass silicon success with reduced time and risk," said Ken Liou, director of UMC's IP and Design Support division, in a statement.

The reference design flow incorporates many of the Galaxy design platform's low power and design-for-manufacturing innovations, including Power Network Synthesis (PNS) and Power Network Analysis (PNA) products, which are used to design power plans at the floorplanning stage.

Synopsys said it has brought several new DFM capabilities to the new 90nm reference design flow, including timing-driven dummy metal insertion to specifically meet UMC's metal density requirements while maintaining timing closure, and automatic redundant via and via farm insertion.

The UMC/Synopsys reference design flow is available now and can be accessed from UMC's website.

- Dylan McGrath
EE Times

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