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Manufacturing moves into design flow

Posted: 01 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:richard goering? clear shape technologies? design for manufacturability? dfm? optical proximity correction?

After spending time with VC companies reviewing business plans for design-for-manufacturability (DFM) startups, Atul Sharan and Yao-Ting Wang decided they could do a better job themselves. So they left the VC world and started Clear Shape Technologies Inc., promising a new approach to modeling IC manufacturing effects.

Clear Shape is preparing technology that will bring "design manufacturability check" models into the IC design flow, along with tools to help optimize designs so they won't have problems with optical proximity correction (opc) or manufacturing. The company promises a fast, accurate and secure way to predict the impact of systematic manufacturing variations without forcing the designer to run OPC or to disrupt established design flows.

Sharan, Clear Shape's president and CEO, was previously VP of marketing and business development at Synopsys Inc. and, before that, a VP at Numerical Technologies Inc. Wang, a consulting professor at Stanford University, was CTO and VP of engineering at Numerical.

Sharan left Synopsys in 2003 and worked for the VC firm Mohr Davidow; Wang, meanwhile, landed at AsiaTech Management. Both turned down a lot of DFM startup proposals because most "were really improving the efficiency of current ret [resolution enhancement technology] and OPC solutions," Sharan said. "That does not make sense from a design perspective."

Along with co-founder Fang-Cheng Chang, VP of engineering for process technology, Sharan and Wang launched Clear Shape in October 2003 and subsequently raised $10 million in venture capital. Nishath Verghese, VP of engineering for design technology, left Cadence Design Systems Inc. to start a power-optimization company that Clear Shape purchased.

Clear Shape's stated mission is to "renew the contract" between design and manufacturing by predicting and reducing systematic manufacturing variations and their impact on design. It does this through a modeling process that claims to capture the entire manufacturing flow, including RET, OPC, lithography and etch effects, and bring these transparently into existing design flows.

The company hasn't announced any products, but is currently in beta sites and is expecting a rollout early next year, Sharan said. Meanwhile, Clear Shape has been describing its approach at industry conferences.

Clear Shape's message is that designers shouldn't have to worry about DFM. "Designers should not have to deal with any statistics or new information that has to do with yield," Sharan said. "They should continue to optimize the constraints they have for timing, power and signal integrity. We provide a platform that takes information from the fab to accurately predict what's going to be in silicon."

Sharan noted that a lot of EDA companies are addressing DFM through techniques such as wire spreading, but that's not where the main problem is. "The big problem is associated with systematic variations due to lithography and etch," he said. Such variations are deterministic rather than random. They may be catastrophic, causing opens or shorts, or parametric, resulting in electrical variations.

To predict systematic variations, Clear Shape has developed technology that collects fab information, runs a testbench through the RET flow and puts data into a model that can be used by the DFM tools that Clear Shape plans to deploy. These "compact models" will come from the fab, as SPICE models do today. They will model both device and interconnect variations.

The models also promise to be encrypted, possibly removing one of the biggest stumbling blocks to DFM: the reluctance of foundries to share yield data with fabless customers. Clear Shape is working with foundries today, Sharan said, although he declined to provide any names.

Clear Shape's tools will run alongside conventional IC layout tools and will optimize designs to avoid OPC or manufacturing problems, Sharan said. "The tool looks through the process window to identify areas where you're going to have a problem for a particular RET-mask-silicon flow and tells you how to fix it," he said. Eventually, Sharan said, the technology may be buried inside correct-by-construction placement or routing tools. He said it can also be used to create "DFM-aware" libraries.

Sharan noted that Clear Shape's tools will work with any design flow, including those from Synopsys, Cadence Design Systems, Mentor Graphics or Magma Design Automation. "We are agnostic about any design tools and RET tools or strategies you're using," he said.

Clear Shape's technology can complement statistical timing analysis, he said, because it can factor out the systematic or deterministic variations, thus reducing the variability that the statistical tool has to analyze. Then the statistical analyzer can focus on random variations. "The problem with statistical timing analysis today is that it lumps random and systematic together," he said.

The 25-person company isn't yet providing detailed product information. "We've worked very hard to conserve cash and we're focusing on R&D, not on marketing," Sharan said. Expect to hear more from Clear Shape in early 2006, he said.

- Richard Goering
EE Times




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