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Synopsys' IC Compiler used in Agere 90nm DSP SoC

Posted: 01 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:soc? 90nm dsp? Synopsys? Agere Systems? IC Compiler?

Synopsys Inc. disclosed that Agere Systems Inc. used Synopsys' IC Compiler next-generation place-and-route system to tape out a 90nm multi-core DSP system-on-chip (SoC) for telecom applications.

The Agere design team needed to reduce routing congestion on the 90nm DSP SoC while meeting timing and power specifications. According to Synopsys, its IC Compiler easily fit into the Agere flow and delivered initial results in just two days. Synopsys added that the new Extended Physical Synthesis architecture in IC Compiler, combined with the tool's multi-threshold capabilities, enabled Agere to concurrently optimize for timing and power, reducing routing congestion and speeding the time to closure.

"We were able to easily deploy IC Compiler and produced better results than we could achieve before. We are encouraged by these excellent results, and are now pursuing IC Compiler deployment across multiple designs," said Jill Bennett, engineering director with Agere's Telecommunications Division,

Antun Domic, SVP and GM, Synopsys Implementation Group, stated, "Agere's tapeout success underscores Synopsys' commitment to help customers reduce their time-to-market and deliver chips with higher performance and yield."




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